nb/intel/nehalem: Use the common mrc cache driver
The common mrc cache driver allows to save the raminit training
results to a separate fmap region which is more manageable than a
cbfsfile.
Change-Id: I25a6d3fe5466d142e3d10429a87b19047040c251
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig
index 6a9d0de..573fdfe 100644
--- a/src/northbridge/intel/nehalem/Kconfig
+++ b/src/northbridge/intel/nehalem/Kconfig
@@ -21,7 +21,7 @@
select TSC_MONOTONIC_TIMER
select INTEL_GMA_ACPI
select RELOCATABLE_RAMSTAGE
- select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE
+ select CACHE_MRC_SETTINGS
select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc
index b5c19ff..acb828c 100644
--- a/src/northbridge/intel/nehalem/Makefile.inc
+++ b/src/northbridge/intel/nehalem/Makefile.inc
@@ -29,14 +29,4 @@
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
-$(obj)/mrc.cache:
- dd if=/dev/zero count=1 \
- bs=$(shell printf "%d" $(CONFIG_MRC_CACHE_SIZE) ) | \
- tr '\000' '\377' > $@
-
-cbfs-files-y += mrc.cache
-mrc.cache-file := $(obj)/mrc.cache
-mrc.cache-align := 0x10000
-mrc.cache-type := mrc_cache
-
endif
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index a2ccbc3..df88ef3 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -43,7 +43,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/intel/speedstep.h>
#include <cpu/intel/turbo.h>
-#include <northbridge/intel/common/mrc_cache.h>
+#include <mrc_cache.h>
#endif
#if !REAL
@@ -91,6 +91,8 @@
u8 largest;
} timing_bounds_t[2][2][2][9];
+#define MRC_CACHE_VERSION 1
+
struct ram_training {
/* [TM][CHANNEL][SLOT][RANK][LANE] */
u16 lane_timings[4][2][2][2][9];
@@ -1741,17 +1743,18 @@
printk (BIOS_SPEW, "[6e8] = %x\n", train.reg_6e8);
/* Save the MRC S3 restore data to cbmem */
- store_current_mrc_cache(&train, sizeof(train));
+ mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION,
+ &train, sizeof(train));
}
#if REAL
static const struct ram_training *get_cached_training(void)
{
- struct mrc_data_container *cont;
- cont = find_current_mrc_cache();
- if (!cont)
+ struct region_device rdev;
+ if (mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION,
+ &rdev))
return 0;
- return (void *)cont->mrc_data;
+ return (void *)rdev_mmap_full(&rdev);
}
#endif