nb/intel/i945: Move boilerplate romstage to a common location
This adds callbacks for mainboard specific init.
Change-Id: Ib67bc492a7b7f02f9b57a52fd6730e16501b436e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36787
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc
index af3c235..585d61b 100644
--- a/src/northbridge/intel/i945/Makefile.inc
+++ b/src/northbridge/intel/i945/Makefile.inc
@@ -20,6 +20,7 @@
ramstage-y += gma.c
ramstage-y += acpi.c
+romstage-y += romstage.c
romstage-y += memmap.c
romstage-y += raminit.c
romstage-y += early_init.c
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index 4dd5379..e9e6f4d 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -375,6 +375,18 @@
u32 decode_igd_memory_size(u32 gms);
u32 decode_tseg_size(const u8 esmramc);
+/* Romstage mainboard callbacks */
+/* Optional: Override the default LPC config. */
+void mainboard_lpc_decode(void);
+/* Optional: Initialize the superio for serial output. */
+void mainboard_superio_config(void);
+/* Optional: mainboard specific init after console init and before raminit. */
+void mainboard_pre_raminit_config(int s3_resume);
+/* Mainboard specific RCBA init. Happens after raminit. */
+void mainboard_late_rcba_config(void);
+/* Optional: mainboard callback to get SPD map */
+void mainboard_get_spd_map(u8 spd_map[4]);
+
#endif /* __ACPI__ */
#endif /* NORTHBRIDGE_INTEL_I945_H */
diff --git a/src/northbridge/intel/i945/romstage.c b/src/northbridge/intel/i945/romstage.c
new file mode 100644
index 0000000..c11a78a
--- /dev/null
+++ b/src/northbridge/intel/i945/romstage.c
@@ -0,0 +1,95 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <cf9_reset.h>
+#include <cpu/x86/lapic.h>
+#include <console/console.h>
+#include <arch/romstage.h>
+#include <northbridge/intel/i945/i945.h>
+#include <northbridge/intel/i945/raminit.h>
+#include <southbridge/intel/i82801gx/i82801gx.h>
+#include <southbridge/intel/common/pmclib.h>
+
+__weak void mainboard_lpc_decode(void)
+{
+}
+
+__weak void mainboard_superio_config(void)
+{
+}
+
+__weak void mainboard_pre_raminit_config(int s3_resume)
+{
+}
+
+__weak void mainboard_get_spd_map(u8 spd_map[4])
+{
+ spd_map[0] = 0x50;
+ spd_map[1] = 0x51;
+ spd_map[2] = 0x52;
+ spd_map[3] = 0x53;
+}
+
+void mainboard_romstage_entry(void)
+{
+ int s3resume = 0;
+ u8 spd_map[4] = {};
+
+ enable_lapic();
+
+ i82801gx_lpc_setup();
+ mainboard_lpc_decode();
+ mainboard_superio_config();
+
+ /* Set up the console */
+ console_init();
+
+ if (MCHBAR16(SSKPD) == 0xCAFE) {
+ system_reset();
+ }
+
+ /* Perform some early chipset initialization required
+ * before RAM initialization can work
+ */
+ i82801gx_early_init();
+ i945_early_initialization();
+
+ s3resume = southbridge_detect_s3_resume();
+
+ /* Enable SPD ROMs and DDR-II DRAM */
+ enable_smbus();
+
+ mainboard_pre_raminit_config(s3resume);
+
+ if (CONFIG(DEBUG_RAM_SETUP))
+ dump_spd_registers();
+
+ mainboard_get_spd_map(spd_map);
+
+ sdram_initialize(s3resume ? 2 : 0, spd_map);
+
+ /* This should probably go away. Until now it is required
+ * and mainboard specific
+ */
+ mainboard_late_rcba_config();
+
+ /* Chipset Errata! */
+ fixup_i945_errata();
+
+ /* Initialize the internal PCIe links before we go into stage2 */
+ i945_late_initialization(s3resume);
+}