sb/intel: Use ACPI_FADT_C2/C3_NOT_SUPPORTED defines
Change-Id: I242e05ee63f46bedbab3a425e922e60f1c749a15
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/src/southbridge/intel/bd82x6x/fadt.c b/src/southbridge/intel/bd82x6x/fadt.c
index f625198..be315af 100644
--- a/src/southbridge/intel/bd82x6x/fadt.c
+++ b/src/southbridge/intel/bd82x6x/fadt.c
@@ -32,8 +32,8 @@
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 16;
/* P_LVLx not used */
- fadt->p_lvl2_lat = 101;
- fadt->p_lvl3_lat = 1001;
+ fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
+ fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
/* P_CNT not supported */
fadt->duty_offset = 0;
fadt->duty_width = 0;
diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c
index 1d640f4..fc3258a 100644
--- a/src/southbridge/intel/i82371eb/fadt.c
+++ b/src/southbridge/intel/i82371eb/fadt.c
@@ -36,8 +36,8 @@
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 4;
- fadt->p_lvl2_lat = 101; /* >100 means c2 not supported */
- fadt->p_lvl3_lat = 1001; /* >1000 means c3 not supported */
+ fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
+ fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */
fadt->duty_width = 3; /* this width is in bits */
fadt->day_alrm = 0x0d; /* rtc CMOS RAM offset */
diff --git a/src/southbridge/intel/ibexpeak/fadt.c b/src/southbridge/intel/ibexpeak/fadt.c
index 13243af..9921b4d 100644
--- a/src/southbridge/intel/ibexpeak/fadt.c
+++ b/src/southbridge/intel/ibexpeak/fadt.c
@@ -32,8 +32,8 @@
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 16;
/* P_LVLx not used */
- fadt->p_lvl2_lat = 101;
- fadt->p_lvl3_lat = 1001;
+ fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
+ fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
/* P_CNT not supported */
fadt->duty_offset = 0;
fadt->duty_width = 0;
diff --git a/src/southbridge/intel/lynxpoint/fadt.c b/src/southbridge/intel/lynxpoint/fadt.c
index 2051223..fc08f01 100644
--- a/src/southbridge/intel/lynxpoint/fadt.c
+++ b/src/southbridge/intel/lynxpoint/fadt.c
@@ -45,8 +45,8 @@
fadt->gpe0_blk_len = 2 * 8;
/* P_LVLx not used */
- fadt->p_lvl2_lat = 101;
- fadt->p_lvl3_lat = 1001;
+ fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
+ fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->duty_offset = 0;
fadt->duty_width = 0;
fadt->day_alrm = 0xd;