soc/amd/*/acpi/northbridge,pci0: don't hide PCI0 root device from OS
Return 0xf from PCI0 _STA method so that bit 2 is set which indicates
that the device should be shown in the user interface. This ports commit
c259d7192806 ("soc/amd/stoney/acpi: Unhide PCI0 root device from OS")
forward from Stoneyridge to the newer AMD SoCs.
TEST=On Mandolin the PCI Express Root Complex now shows up in the device
manager on Windows 10 and when switching the view to 'devices by
connection', all PCI(e) devices are shown below it.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4155556dc5df8f163fe06aa6719fadbb2684cc19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74949
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/amd/cezanne/acpi/pci0.asl b/src/soc/amd/cezanne/acpi/pci0.asl
index 93bfb1f..fb02a02 100644
--- a/src/soc/amd/cezanne/acpi/pci0.asl
+++ b/src/soc/amd/cezanne/acpi/pci0.asl
@@ -10,7 +10,7 @@
}
Method(_STA, 0, NotSerialized) {
- Return(0x0B) /* Status is visible */
+ Return(0x0f) /* Status is visible */
}
/* Operating System Capabilities Method */
diff --git a/src/soc/amd/glinda/acpi/pci0.asl b/src/soc/amd/glinda/acpi/pci0.asl
index 2f7e0ba..925f853 100644
--- a/src/soc/amd/glinda/acpi/pci0.asl
+++ b/src/soc/amd/glinda/acpi/pci0.asl
@@ -12,7 +12,7 @@
}
Method(_STA, 0, NotSerialized) {
- Return(0x0B) /* Status is visible */
+ Return(0x0f) /* Status is visible */
}
/* Operating System Capabilities Method */
diff --git a/src/soc/amd/mendocino/acpi/pci0.asl b/src/soc/amd/mendocino/acpi/pci0.asl
index 5bf2f3e..5cc6f9f 100644
--- a/src/soc/amd/mendocino/acpi/pci0.asl
+++ b/src/soc/amd/mendocino/acpi/pci0.asl
@@ -12,7 +12,7 @@
}
Method(_STA, 0, NotSerialized) {
- Return(0x0B) /* Status is visible */
+ Return(0x0f) /* Status is visible */
}
/* Operating System Capabilities Method */
diff --git a/src/soc/amd/phoenix/acpi/pci0.asl b/src/soc/amd/phoenix/acpi/pci0.asl
index 665fe30..345b66e 100644
--- a/src/soc/amd/phoenix/acpi/pci0.asl
+++ b/src/soc/amd/phoenix/acpi/pci0.asl
@@ -12,7 +12,7 @@
}
Method(_STA, 0, NotSerialized) {
- Return(0x0B) /* Status is visible */
+ Return(0x0f) /* Status is visible */
}
/* Operating System Capabilities Method */
diff --git a/src/soc/amd/picasso/acpi/northbridge.asl b/src/soc/amd/picasso/acpi/northbridge.asl
index 6850a1a..99d04b5 100644
--- a/src/soc/amd/picasso/acpi/northbridge.asl
+++ b/src/soc/amd/picasso/acpi/northbridge.asl
@@ -15,7 +15,7 @@
Method(_STA, 0, NotSerialized)
{
- Return(0x0B) /* Status is visible */
+ Return(0x0f) /* Status is visible */
}
/* PCI Routing Table */