commit | db8a97a0e01fd87ab3f8e6893f8e0ccf98986e27 | [log] [tgz] |
---|---|---|
author | Sridhar Siricilla <sridhar.siricilla@intel.com> | Fri Apr 29 15:13:38 2022 +0530 |
committer | Felix Held <felix-coreboot@felixheld.de> | Wed May 25 18:56:08 2022 +0000 |
tree | 59f1ee336f32be72c516a8937e4d28afac27529e | |
parent | 616c07c87f3e7acdab2ec10fc95579cf53fca3a6 [diff] |
soc/intel/common: Skip sending DISCONNECT IPC command The patch skips sending DISCONNECT IPC command to PMC if system resumes from S3. coreboot notice DISCONNECT IPC command getting timedout during S3 resume if system has AC connected behind Type-C hub. This impacts system resume time. Please refer TA# 730910 for more information. coreboot need not send the DISCONNECT IPC command when system resumes from S3 state. TEST=Verified system boots to OS and verfied below tests on Gimble 1. coreboot doesn't send the DISCONNECT during S3 resume 2. After S3 resume, system detects the pen drive with Superspeed 3. After system resumes from S3, hot-plug the pen drive, system detects the pen drive 3. System sends IPC commands when system boots from S0 or S5. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I6ad006ae8677919c7dfeca8eec0af11454a2e89d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you're feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.