| commit | db6d1983da9559b3910e6833be68029f73c0f258 | [log] [tgz] |
|---|---|---|
| author | Evan Green <evgreen@chromium.org> | Fri Apr 22 10:55:15 2022 -0700 |
| committer | Felix Held <felix-coreboot@felixheld.de> | Wed Apr 27 12:24:40 2022 +0000 |
| tree | d11f60a2d4442492e3cd731ff6864508ffeed2f0 | |
| parent | e6c677ce94960f983c9246d190a28dc405152d36 [diff] |
soc/intel/common/block/acpi: Fill PEP S0 mask on failure There is a bug floating around where communciation with the PMC fails after transitions through S3/S4/S5. This CL does not address that issue. However in working with error cases presented by a failing PMC, we're forced into an early return in read_pmc_lpm_requirements(), which sets up _DSM buffers in the SSDT for the PEP device. The function itself returns void, so the error is swallowed regardless. However returning early is not the appropriate action because it causes the size of the buffer written into the _DSM method to change. This causes the SSDT to change size and layout across an S3 or S4 transition, which results in mayhem in the kernel, as the kernel is not expecting these tables to change out from under it. Instead of returning early, it's better to simply print the error and keep going, attaching a zeroed out buffer for the substate requirements. This results in an empty requirements mask for all states. From what I can see in the kernel this is no more broken than today's behavior, as this buffer seems to only be used for printing a debugfs file. In fact in this particular case the kernel doesn't even notice, as this buffer is copied out at boot, and not refreshed at resume. BUG=b:230031158 TEST=hibernate and resume on Primus4ES Signed-off-by: Evan Green <evgreen@chromium.org> Change-Id: Ibe35d50b350b1b96dea313dfcbd00745970c16ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/63790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).Optional:
make menuconfig and make nconfig)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
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This makes the resulting coreboot images licensed under the GPL, version 2.