soc/intel: convert XTAL frequency constant to Kconfig
This converts the constant for the XTAL frequency to a Kconfig option.
Change-Id: I1382dd274eeb9cb748f94c34f5d9a83880624c18
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index dc9e823..1a3f072 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -136,6 +136,9 @@
int
default 120
+config CPU_XTAL_HZ
+ default 38400000
+
config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
int
default 133
diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c
index ee8051d..e6a21c1 100644
--- a/src/soc/intel/alderlake/cpu.c
+++ b/src/soc/intel/alderlake/cpu.c
@@ -111,15 +111,17 @@
static void enable_pm_timer_emulation(void)
{
- /* ACPI PM timer emulation */
msr_t msr;
+
+ if (!CONFIG_CPU_XTAL_HZ)
+ return;
+
/*
* The derived frequency is calculated as follows:
- * (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
- * Back solve the multiplier so the 3.579545MHz ACPI timer
- * frequency is used.
+ * (clock * msr[63:32]) >> 32 = target frequency.
+ * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used.
*/
- msr.hi = (3579545ULL << 32) / CTC_FREQ;
+ msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ;
/* Set PM1 timer IO port and enable */
msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
diff --git a/src/soc/intel/alderlake/include/soc/cpu.h b/src/soc/intel/alderlake/include/soc/cpu.h
index 3c11183..71c2f47 100644
--- a/src/soc/intel/alderlake/include/soc/cpu.h
+++ b/src/soc/intel/alderlake/include/soc/cpu.h
@@ -19,7 +19,4 @@
#define C9_POWER 0xc8
#define C10_POWER 0xc8
-/* Common Timer Copy (CTC) frequency - 38.4MHz. */
-#define CTC_FREQ 38400000
-
#endif
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index c1b5252..69d42bd 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -157,6 +157,9 @@
int
default 100
+config CPU_XTAL_HZ
+ default 19200000
+
config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
int
default 133
diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h
index 490820c..38b830a 100644
--- a/src/soc/intel/apollolake/include/soc/cpu.h
+++ b/src/soc/intel/apollolake/include/soc/cpu.h
@@ -6,9 +6,6 @@
#include <cpu/x86/msr.h>
#include <intelblocks/msr.h>
-/* Common Timer Copy (CTC) frequency - 19.2MHz. */
-#define CTC_FREQ 19200000
-
struct device;
void apollolake_init_cpus(struct device *dev);
void mainboard_devtree_update(struct device *dev);
diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c
index c6d2eec..e0de93e 100644
--- a/src/soc/intel/apollolake/pmutil.c
+++ b/src/soc/intel/apollolake/pmutil.c
@@ -180,15 +180,17 @@
void enable_pm_timer_emulation(void)
{
- /* ACPI PM timer emulation */
msr_t msr;
+
+ if (!CONFIG_CPU_XTAL_HZ)
+ return;
+
/*
* The derived frequency is calculated as follows:
- * (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
- * Back solve the multiplier so the 3.579545MHz ACPI timer
- * frequency is used.
+ * (clock * msr[63:32]) >> 32 = target frequency.
+ * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used.
*/
- msr.hi = (3579545ULL << 32) / CTC_FREQ;
+ msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ;
/* Set PM1 timer IO port and enable */
msr.lo = EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + R_ACPI_PM1_TMR);
wrmsr(MSR_EMULATE_PM_TIMER, msr);
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index dc2be28..24f64b1 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -245,6 +245,9 @@
int
default 120
+config CPU_XTAL_HZ
+ default 24000000
+
config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
int
default 216
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c
index ddedb3f..0622034 100644
--- a/src/soc/intel/cannonlake/cpu.c
+++ b/src/soc/intel/cannonlake/cpu.c
@@ -114,19 +114,22 @@
{
msr_t msr;
+ if (!CONFIG_CPU_XTAL_HZ)
+ return;
+
/*
* The derived frequency is calculated as follows:
- * (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
- * Back solve the multiplier so the 3.579545MHz ACPI timer
- * frequency is used.
+ * (clock * msr[63:32]) >> 32 = target frequency.
+ * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used.
*/
- msr.hi = (3579545ULL << 32) / CTC_FREQ;
+ msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ;
/* Set PM1 timer IO port and enable */
msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
wrmsr(MSR_EMULATE_PM_TIMER, msr);
}
+
static void set_energy_perf_bias(u8 policy)
{
msr_t msr;
diff --git a/src/soc/intel/cannonlake/include/soc/cpu.h b/src/soc/intel/cannonlake/include/soc/cpu.h
index b356d3a9..3542a2b 100644
--- a/src/soc/intel/cannonlake/include/soc/cpu.h
+++ b/src/soc/intel/cannonlake/include/soc/cpu.h
@@ -22,9 +22,6 @@
#define C9_POWER 0xc8
#define C10_POWER 0xc8
-/* Common Timer Copy (CTC) frequency - 24MHz. */
-#define CTC_FREQ 24000000
-
#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \
(((1 << ((base)*5)) * (limit)) / 1000)
#define C_STATE_LATENCY_FROM_LAT_REG(reg) \
diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig
index 9e95a8a..9023b58 100644
--- a/src/soc/intel/common/block/cpu/Kconfig
+++ b/src/soc/intel/common/block/cpu/Kconfig
@@ -99,6 +99,11 @@
it would get enabled. If CPU supports MKTME, this same config option
enables MKTME.
+config CPU_XTAL_HZ
+ int
+ help
+ Base clock which virtually everything runs on.
+
config CPU_SUPPORTS_PM_TIMER_EMULATION
bool
default n
diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig
index 40770d0..05077ad 100644
--- a/src/soc/intel/elkhartlake/Kconfig
+++ b/src/soc/intel/elkhartlake/Kconfig
@@ -133,6 +133,9 @@
int
default 120
+config CPU_XTAL_HZ
+ default 38400000
+
config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
int
default 133
diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c
index 382bbf7..271d244 100644
--- a/src/soc/intel/elkhartlake/cpu.c
+++ b/src/soc/intel/elkhartlake/cpu.c
@@ -105,15 +105,17 @@
static void enable_pm_timer_emulation(void)
{
- /* ACPI PM timer emulation */
msr_t msr;
+
+ if (!CONFIG_CPU_XTAL_HZ)
+ return;
+
/*
* The derived frequency is calculated as follows:
- * (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
- * Back solve the multiplier so the 3.579545MHz ACPI timer
- * frequency is used.
+ * (clock * msr[63:32]) >> 32 = target frequency.
+ * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used.
*/
- msr.hi = (3579545ULL << 32) / CTC_FREQ;
+ msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ;
/* Set PM1 timer IO port and enable */
msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
diff --git a/src/soc/intel/elkhartlake/include/soc/cpu.h b/src/soc/intel/elkhartlake/include/soc/cpu.h
index 6ee34f2..ec3cd3e 100644
--- a/src/soc/intel/elkhartlake/include/soc/cpu.h
+++ b/src/soc/intel/elkhartlake/include/soc/cpu.h
@@ -21,9 +21,6 @@
#define C9_POWER 0xc8
#define C10_POWER 0xc8
-/* Common Timer Copy (CTC) frequency - 38.4MHz. */
-#define CTC_FREQ 38400000
-
#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \
(((1 << ((base)*5)) * (limit)) / 1000)
#define C_STATE_LATENCY_FROM_LAT_REG(reg) \
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig
index 027ed7d..21da528 100644
--- a/src/soc/intel/icelake/Kconfig
+++ b/src/soc/intel/icelake/Kconfig
@@ -127,6 +127,9 @@
int
default 120
+config CPU_XTAL_HZ
+ default 38400000
+
config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
int
default 133
diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c
index 2823fd7..e76f61f 100644
--- a/src/soc/intel/icelake/cpu.c
+++ b/src/soc/intel/icelake/cpu.c
@@ -105,15 +105,17 @@
static void enable_pm_timer_emulation(void)
{
- /* ACPI PM timer emulation */
msr_t msr;
+
+ if (!CONFIG_CPU_XTAL_HZ)
+ return;
+
/*
* The derived frequency is calculated as follows:
- * (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
- * Back solve the multiplier so the 3.579545MHz ACPI timer
- * frequency is used.
+ * (clock * msr[63:32]) >> 32 = target frequency.
+ * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used.
*/
- msr.hi = (3579545ULL << 32) / CTC_FREQ;
+ msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ;
/* Set PM1 timer IO port and enable */
msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
diff --git a/src/soc/intel/icelake/include/soc/cpu.h b/src/soc/intel/icelake/include/soc/cpu.h
index a231333..5dc22de 100644
--- a/src/soc/intel/icelake/include/soc/cpu.h
+++ b/src/soc/intel/icelake/include/soc/cpu.h
@@ -21,9 +21,6 @@
#define C9_POWER 0xc8
#define C10_POWER 0xc8
-/* Common Timer Copy (CTC) frequency - 38.4MHz. */
-#define CTC_FREQ 38400000
-
#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \
(((1 << ((base)*5)) * (limit)) / 1000)
#define C_STATE_LATENCY_FROM_LAT_REG(reg) \
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index ba7e621..d5adc60 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -137,6 +137,9 @@
int
default 133
+config CPU_XTAL_HZ
+ default 38400000
+
config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
int
default 3
diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c
index 3a50929..1944e5c 100644
--- a/src/soc/intel/jasperlake/cpu.c
+++ b/src/soc/intel/jasperlake/cpu.c
@@ -105,15 +105,17 @@
static void enable_pm_timer_emulation(void)
{
- /* ACPI PM timer emulation */
msr_t msr;
+
+ if (!CONFIG_CPU_XTAL_HZ)
+ return;
+
/*
* The derived frequency is calculated as follows:
- * (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
- * Back solve the multiplier so the 3.579545MHz ACPI timer
- * frequency is used.
+ * (clock * msr[63:32]) >> 32 = target frequency.
+ * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used.
*/
- msr.hi = (3579545ULL << 32) / CTC_FREQ;
+ msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ;
/* Set PM1 timer IO port and enable */
msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
diff --git a/src/soc/intel/jasperlake/include/soc/cpu.h b/src/soc/intel/jasperlake/include/soc/cpu.h
index c61f2ee..40cebd4 100644
--- a/src/soc/intel/jasperlake/include/soc/cpu.h
+++ b/src/soc/intel/jasperlake/include/soc/cpu.h
@@ -21,9 +21,6 @@
#define C9_POWER 0xc8
#define C10_POWER 0xc8
-/* Common Timer Copy (CTC) frequency - 38.4MHz. */
-#define CTC_FREQ 38400000
-
#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \
(((1 << ((base)*5)) * (limit)) / 1000)
#define C_STATE_LATENCY_FROM_LAT_REG(reg) \
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 14d4fa1..55e74cd 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -241,6 +241,9 @@
int
default 120
+config CPU_XTAL_HZ
+ default 24000000
+
config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
int
default SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index f1b40f6..5ec0023 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -169,15 +169,17 @@
*/
static void enable_pm_timer_emulation(void)
{
- /* ACPI PM timer emulation */
msr_t msr;
+
+ if (!CONFIG_CPU_XTAL_HZ)
+ return;
+
/*
* The derived frequency is calculated as follows:
- * (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
- * Back solve the multiplier so the 3.579545MHz ACPI timer
- * frequency is used.
+ * (clock * msr[63:32]) >> 32 = target frequency.
+ * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used.
*/
- msr.hi = (3579545ULL << 32) / CTC_FREQ;
+ msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ;
/* Set PM1 timer IO port and enable */
msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h
index 740b3d3..473068c 100644
--- a/src/soc/intel/skylake/include/soc/cpu.h
+++ b/src/soc/intel/skylake/include/soc/cpu.h
@@ -25,9 +25,6 @@
#define C9_POWER 0xc8
#define C10_POWER 0xc8
-/* Common Timer Copy (CTC) frequency - 24MHz. */
-#define CTC_FREQ 24000000
-
#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \
(((1 << ((base)*5)) * (limit)) / 1000)
#define C_STATE_LATENCY_FROM_LAT_REG(reg) \
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 0021da5..2b5f0ba 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -138,6 +138,9 @@
int
default 120
+config CPU_XTAL_HZ
+ default 38400000
+
config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
int
default 133
diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c
index be056fb..1a5165d 100644
--- a/src/soc/intel/tigerlake/cpu.c
+++ b/src/soc/intel/tigerlake/cpu.c
@@ -111,15 +111,17 @@
static void enable_pm_timer_emulation(void)
{
- /* ACPI PM timer emulation */
msr_t msr;
+
+ if (!CONFIG_CPU_XTAL_HZ)
+ return;
+
/*
* The derived frequency is calculated as follows:
- * (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
- * Back solve the multiplier so the 3.579545MHz ACPI timer
- * frequency is used.
+ * (clock * msr[63:32]) >> 32 = target frequency.
+ * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used.
*/
- msr.hi = (3579545ULL << 32) / CTC_FREQ;
+ msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ;
/* Set PM1 timer IO port and enable */
msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
diff --git a/src/soc/intel/tigerlake/include/soc/cpu.h b/src/soc/intel/tigerlake/include/soc/cpu.h
index 47a41eb..2d6336a 100644
--- a/src/soc/intel/tigerlake/include/soc/cpu.h
+++ b/src/soc/intel/tigerlake/include/soc/cpu.h
@@ -21,7 +21,4 @@
#define C9_POWER 0xc8
#define C10_POWER 0xc8
-/* Common Timer Copy (CTC) frequency - 38.4MHz. */
-#define CTC_FREQ 38400000
-
#endif