mb/google/rex: Change GPP_A17 programming
To match byra commit 7c2514fc072f95eed6483518811fb6c39f780f5b (mb/google/brya: Change GPP_F17 programming), update A17 pad
configuration to the APIC only.
TEST=Verified booting to OS on Google/Rex.
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: Ie9f071dc4a2755dd1f396e2afe730ead66bb1dd0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67183
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/google/rex/variants/rex0/gpio.c b/src/mainboard/google/rex/variants/rex0/gpio.c
index 75e4062..8f4ea6c 100644
--- a/src/mainboard/google/rex/variants/rex0/gpio.c
+++ b/src/mainboard/google/rex/variants/rex0/gpio.c
@@ -34,7 +34,8 @@
PAD_CFG_GPO(GPP_A15, 1, DEEP),
/* GPP_A16 : GPP_A16 ==> ESPI_SOC_ALERT_L configured on reset, do not touch */
/* GPP_A17 : [] ==> EC_SOC_INT_ODL */
- PAD_CFG_GPI_IRQ_WAKE(GPP_A17, NONE, PLTRST, LEVEL, INVERT),
+ PAD_CFG_GPI_APIC_LOCK(GPP_A17, NONE, LEVEL, INVERT, LOCK_CONFIG),
+
/* GPP_A18 : [] ==> CAM_PSW_L */
PAD_CFG_GPI_INT_LOCK(GPP_A18, NONE, EDGE_BOTH, LOCK_CONFIG),
/* GPP_A19 : [] ==> EN_PP3300_SSD */
@@ -388,9 +389,6 @@
/* GPP_E13 : [] ==> MEM_CH_SEL */
PAD_CFG_GPI(GPP_E13, NONE, DEEP),
- /* GPP_A17 : [] ==> EC_SOC_INT_ODL */
- PAD_CFG_GPI_APIC_LOCK(GPP_A17, NONE, LEVEL, INVERT, LOCK_CONFIG),
-
/* GPP_A20 : [] ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_A20, 0, DEEP),