nb/intel/pineview: Select 1M TSEG
With the only valid GTT setting being 1M, TSEG_BASE can only be
aligned to TSEG_SIZE if it is also 1M. This alignment requirement
comes from the desire to use SMRR to protect the SMM RAM.
Tested on Foxconn D41S.
Change-Id: Ibd879529923a1676f2e78500797a52d8a37b8eef
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c
index 3413cc1..ee19b61 100644
--- a/src/northbridge/intel/pineview/raminit.c
+++ b/src/northbridge/intel/pineview/raminit.c
@@ -2032,9 +2032,9 @@
gttsize = ggc_to_gtt[(ggc & 0x300) >> 8];
tom = s->channel_capacity[0];
- /* TSEG 2M, This amount can easily be covered by SMRR MTRR's,
- which requires to have TSEG_BASE aligned to TSEG_SIZE. */
- tsegsize = 0x2;
+ /* with GTT always being 1M, TSEG 1M is the only setting that can
+ be covered by SMRR which has alignment requirements. */
+ tsegsize = 0x1;
mmiosize = 0x400; // 1GB
reclaim = false;
@@ -2071,7 +2071,7 @@
u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC);
reg8 &= ~0x7;
- reg8 |= (1 << 1) | (1 << 0); /* 2M and TSEG_Enable */
+ reg8 |= (0 << 1) | (1 << 0); /* 1M and TSEG_Enable */
pci_write_config8(PCI_DEV(0, 0, 0), ESMRAMC, reg8);
printk(BIOS_DEBUG, "GBSM (igd) = verified %08x (written %08x)\n",