arch/riscv: Delegate exceptions to supervisor mode if appropriate
Change-Id: I1c8127412af0f9acc5b5520dc324ac145e59a4bd
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16160
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index bea552d..98b7edc 100644
--- a/src/arch/riscv/virtual_memory.c
+++ b/src/arch/riscv/virtual_memory.c
@@ -208,4 +208,14 @@
clear_csr(mip, MIP_MSIP);
set_csr(mie, MIP_MSIP);
+
+ /* Configure which exception causes are delegated to supervisor mode */
+ set_csr(medeleg, (1 << CAUSE_MISALIGNED_FETCH)
+ | (1 << CAUSE_FAULT_FETCH)
+ | (1 << CAUSE_ILLEGAL_INSTRUCTION)
+ | (1 << CAUSE_BREAKPOINT)
+ | (1 << CAUSE_FAULT_LOAD)
+ | (1 << CAUSE_FAULT_STORE)
+ | (1 << CAUSE_USER_ECALL)
+ );
}