soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage
This patch sets up cse_fw_sync() call in the romstage. The cse_fw_sync()
must be called after DRAM initialization.
BUG=b:174694480
Test=Verified on Tigerlake platform
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ib485a4d1d15989b162105deb32bb317d7a0f2856
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48281
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/tigerlake/romstage/romstage.c b/src/soc/intel/tigerlake/romstage/romstage.c
index 1fa6c2d..8b7dc23 100644
--- a/src/soc/intel/tigerlake/romstage/romstage.c
+++ b/src/soc/intel/tigerlake/romstage/romstage.c
@@ -135,6 +135,17 @@
s3wake = pmc_fill_power_state(ps) == ACPI_S3;
fsp_memory_init(s3wake);
pmc_set_disb();
- if (!s3wake)
+ if (!s3wake) {
+ /*
+ * cse_fw_sync() must be called after DRAM initialization as
+ * HMRFPO_ENABLE HECI command (which is used by cse_fw_sync())
+ * is expected to be executed after DRAM initialization.
+ */
+
+ if (CONFIG(SOC_INTEL_CSE_LITE_SKU))
+ cse_fw_sync();
+
save_dimm_info();
+ }
+
}