nb/intel/haswell: Confine `pei_data` uses to raminit.c
Reorganize romstage.c to resemble sandybridge, and move everything that
needs `pei_data` into raminit.c function `perform_raminit`. Barring USB
settings, coreboot code no longer depends on pei_data.h definitions. It
still depends on MRC, though. For now.
Tested on Asrock B85M Pro4, still boots and still resumes from S3.
Change-Id: I433f88db5fe7a7533ab6837015647ec31fb45e88
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51449
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h
index ff95a45..7eb3980 100644
--- a/src/northbridge/intel/haswell/raminit.h
+++ b/src/northbridge/intel/haswell/raminit.h
@@ -20,10 +20,6 @@
/* Mainboard callback to fill in the SPD addresses in MRC format */
void mb_get_spd_map(struct spd_info *spdi);
-void sdram_initialize(struct pei_data *pei_data);
-void setup_sdram_meminfo(struct pei_data *pei_data);
-
-/* save_mrc_data() must be called after cbmem has been initialized. */
-void save_mrc_data(struct pei_data *pei_data);
+void perform_raminit(const int s3resume);
#endif /* RAMINIT_H */