commit d907a3402e347633bac09013050a3d290c27d1f8
author Aaron Durbin <adurbin@chromium.org> Thu Jan 30 22:20:01 2014 -0600
committer Aaron Durbin <adurbin@google.com> Tue Feb 11 22:23:15 2014 +0100
tree 1953b397aafc0816d2e1ed332ba06aedee98b88f
parent 6ecdb68562989aec1362e3a99f3ed2e0012e1191

amd/cimx: fix sb(8|9)00 NULL type redefine

It is inappropriate for chipset code to be redefining
types -- especially NULL to a non-pointer type. There's
only one non-straight forward change. A condition
being checked was '!ptr_type == NULL' (0 as int). That
check is actually 'ptr_type != NULL'.

Change-Id: Iab5733e5a573baba6fec94e0c955ba4fad72c836
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5088
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

src/vendorcode/amd/cimx/sb800/SATA.c

diff --git a/src/vendorcode/amd/cimx/sb800/SATA.c b/src/vendorcode/amd/cimx/sb800/SATA.c
index 5966ec8..a301208 100644
--- a/src/vendorcode/amd/cimx/sb800/SATA.c
+++ b/src/vendorcode/amd/cimx/sb800/SATA.c
@@ -258,7 +258,7 @@
   UINT16    i;
   SATAPHYSETTING  *pPhyTable;
 
-  ddTempVar = NULL;
+  ddTempVar = 0;
   // BIT0 Enable write access to PCI header (reg 08h-0Bh) by setting SATA PCI register 40h
   // BIT4: Disable fast boot
   RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0 + BIT2 + BIT4);
@@ -292,17 +292,17 @@
     //Set PATA controller to native mode
     RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG09), AccWidthUint8 | S3_SAVE, 0x00, 0x08F);
   }
-  if (pConfig->BuildParameters.IdeSsid != NULL ) {
+  if (pConfig->BuildParameters.IdeSsid != 0 ) {
     RWPCI ((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.IdeSsid);
   }
   // SATA Controller Class ID & SSID
   pDeviceIdptr = (UINT16 *) FIXUP_PTR (&sataDeviceIDTable[0]);
-  if ( pConfig->BuildParameters.SataIDESsid != NULL ) {
+  if ( pConfig->BuildParameters.SataIDESsid != 0 ) {
     ddTempVar = pConfig->BuildParameters.SataIDESsid;
   }
   dwDeviceId = pDeviceIdptr[dbValue];
   if ( pConfig->SataClass == RAID_MODE) {
-    if ( pConfig->BuildParameters.SataRAID5Ssid != NULL ) {
+    if ( pConfig->BuildParameters.SataRAID5Ssid != 0 ) {
       ddTempVar = pConfig->BuildParameters.SataRAID5Ssid;
     }
     dwDeviceId = V_SB_SATA_RAID5_DID;
@@ -310,19 +310,19 @@
     getEfuseStatus (&pValue);
     if (( pValue & SATA_EFUSE_BIT ) || ( pConfig->SataForceRaid == 1 )) {
       dwDeviceId = V_SB_SATA_RAID_DID;
-      if ( pConfig->BuildParameters.SataRAIDSsid != NULL ) {
+      if ( pConfig->BuildParameters.SataRAIDSsid != 0 ) {
         ddTempVar = pConfig->BuildParameters.SataRAIDSsid;
       }
     }
   }
   if ( ((pConfig->SataClass) == AHCI_MODE) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE) ||
     ((pConfig->SataClass) == AHCI_MODE_4394) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE_4394) ) {
-    if ( pConfig->BuildParameters.SataAHCISsid != NULL ) {
+    if ( pConfig->BuildParameters.SataAHCISsid != 0 ) {
       ddTempVar = pConfig->BuildParameters.SataAHCISsid;
     }
   }
   RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, dwDeviceId);
-  if ( ddTempVar != NULL ) {
+  if ( ddTempVar != 0 ) {
     RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG2C, AccWidthUint32 | S3_SAVE, 0x00, ddTempVar);
   }
   // SATA IRQ Resource