tree 20c62d4d6ff94ede297e9b4dd51e0e71f35954da
parent dc0bdbab2df7ff8c89b0e1325a60ce994ee6bf43
author Marc Jones <marcj303@gmail.com> 1327977045 -0700
committer Marc Jones <marcj303@gmail.com> 1329712646 +0100

Fix MTRR TOM2 WB cache setup for AMD CPUs > revF.

The MTRR check for WB TOM2 setting was only checking revF, not extended family
revisions. All families above revf indicate 0xf in the family field and have
additional bits in the extended family field.

Change-Id: I93d719789acda6b7c42de7fd6d4bad2da866a25f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/627
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>