commit | 756f51b66257a5af7789c06156217d6f0319b457 | [log] [tgz] |
---|---|---|
author | Timofey Komarov <happycorsair@yandex.ru> | Tue Apr 27 10:54:34 2021 +0300 |
committer | Nico Huber <nico.h@gmx.de> | Sat May 01 18:03:18 2021 +0000 |
tree | ad1db6b927334f3c380a01d8dc04df2970e9a370 | |
parent | 7e7d27bf4b5b846456763c606315521548599005 [diff] |
soc/intel/skylake: Add Kconfig option for LGA1151v2 Provide a SOC_INTEL_SKYLAKE_LGA1151_V2 option to select correct defaults for the combination of a Union Point PCH with LGA1151v2. As of the year 2021 it's common for motherboards with Z370, H310C or B365 PCHs, which are meant to be paired with Coffee Lake CPUs. Intel provides AmberLakeFspBinPkg to support this combination, which implements Intel FSP External Architecture Specification v2.1. Details: 1) Provide SOC_INTEL_SKYLAKE_LGA1151_V2 option that selects PLATFORM_USES_FSP2_1, SOC_INTEL_COMMON_SKYLAKE_BASE and SKYLAKE_SOC_PCH_H. 2) Add Amberlake FSP support. If SOC_INTEL_SKYLAKE_LGA1151_V2 is set, use AbmerLakeFspBinPkg instead of KabylakeFspBinPkg. 3) Enable Coffee Lake CPUs support. If SOC_INTEL_SKYLAKE_LGA1151_V2 is set, select MAINBOARD_SUPPORTS_COFFEELAKE_CPU. 4) Increase stack and heap size in CAR. If FSP_USES_CB_STACK is set (it's selected by PLATFORM_USES_FSP2_1), update DCACHE_BSP_STACK_SIZE and FSP_TEMP_RAM_SIZE values. 5) Update maximal number of supported CPUs. If MAINBOARD_SUPPORTS_COFFEELAKE_CPU is set, set MAX_CPUS to 16. Signed-off-by: Timofey Komarov <happycorsair@yandex.ru> Change-Id: I7b6b9c676da55088cb5a12a218ea58d349ee440c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you're feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.