soc/intel/jasperlake: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I78f091e0d3d17fcfc60cd54721b34d143cbe2d86
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
diff --git a/src/soc/intel/jasperlake/bootblock/pch.c b/src/soc/intel/jasperlake/bootblock/pch.c
index 8e3f135..f73c57b 100644
--- a/src/soc/intel/jasperlake/bootblock/pch.c
+++ b/src/soc/intel/jasperlake/bootblock/pch.c
@@ -45,22 +45,21 @@
static void soc_config_pwrmbase(void)
{
uint32_t reg32;
+ uint16_t reg16;
/*
* Assign Resources to PWRMBASE
* Clear BIT 1-2 Command Register
*/
- reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND);
- reg32 &= ~(PCI_COMMAND_MEMORY);
- pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32);
+ reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND);
+ reg16 &= ~(PCI_COMMAND_MEMORY);
+ pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16);
/* Program PWRM Base */
pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
/* Enable Bus Master and MMIO Space */
- reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND);
- reg32 |= PCI_COMMAND_MEMORY;
- pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32);
+ pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY);
/* Enable PWRM in PMC */
reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL));