tree 190304f658c214a0ed963df02e95f690d1b485f7
parent 2f5183c7af57bdefc88999bba62896bbcfe606c6
author Furquan Shaikh <furquan@google.com> 1589069928 -0700
committer Furquan Shaikh <furquan@google.com> 1589309978 +0000

soc/amd/common/block/lpc: Split lpc_set_spibase() into two functions

This change splits lpc_set_spibase() into two separate functions:
lpc_set_spibase() - Sets MMIO base address for SPI controller and eSPI
controller (if supported by platforms)
lpc_enable_spi_rom() - Enables SPI ROM

This split is done to allow setting of MMIO base independent of ROM
enable bits. On platforms like Picasso, eSPI base is determined by the
same register and hence eSPI can set the BAR without having to touch
the enable bits.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I3f270ba1745b4bb8a403f00cd069a02e21d444be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>