tree e277a83bfba77437733bf4a12a61f8fe633c2ab8
parent 9d678f2e56ece95bd9289ad05ec8670d6329ff16
author Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> 1577482081 -0800
committer Patrick Georgi <pgeorgi@google.com> 1579707792 +0000

soc/intel/tigerlake: Update fsp_params for TGL

Add initial fsp upd settings for TGL, both romstage and ramstage upd's to
support basic build and boot of TGL RVP.
    - Add Silicon upd settings which includes
      * Serial IO/UART settings
      * Graphics settings
      * USB2/USB3 settings
    - Add Romstage upd settings which includes
      * Pcie Root port settings
      * IGD initialization
      * Hyper Threading settings
      * SMBus controller settings
      * Debug probe settings

BUG=none
BRANCH=none
TEST=Build and boot Tigerlake rvp board

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I16df66451fd3a681df1222d283d97dd6bdaff0e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37960
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>