Some more DIMM0 related cleanups and deduplication.
- VIA VT8235: Do the shift in smbus_read_byte() as all other chipsets do.
- spd.h: Move RC00-RC63 #defines here, they were duplicated in lots of
romstage.c files and lots of spd_addr.h files. Don't even bother for
those spd_addr.h which aren't even actually used, drop them right away.
- Replace various 0x50 hardcoded numbers with DIMM0, 0x51 with DIMM1,
and 0xa0 with (DIMM0 << 1) where appropriate.
- Various debug.c files: Replace SMBUS_MEM_DEVICE_START with DIMM0,
SMBUS_MEM_DEVICE_END with DIMM7, and drop useless SMBUS_MEM_DEVICE_INC.
- VIA VX800: Drop unused SMBUS_ADDR_CH* #defines.
- VIA VT8623: Do the shift in smbus_read_byte() as all other chipsets do.
Then, replace 0xa0 (which now becomes 0x50) with DIMM0.
- alix1c/romstage.c, alix2d/romstage.c: Adapt to recent bit shift changes.
- Various files: Drop DIMM_SPD_BASE and/or replace it with DIMM0.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/src/northbridge/intel/i440bx/debug.c b/src/northbridge/intel/i440bx/debug.c
index d574873..1d8cbf6 100644
--- a/src/northbridge/intel/i440bx/debug.c
+++ b/src/northbridge/intel/i440bx/debug.c
@@ -7,7 +7,7 @@
print_debug("\n");
for(i = 0; i < DIMM_SOCKETS; i++) {
unsigned device;
- device = DIMM_SPD_BASE + i;
+ device = DIMM0 + i;
if (device) {
int j;
print_debug("dimm: ");
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index 9a5968d..205d40f 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -616,7 +616,7 @@
reg = pci_read_config8(NB, DRAMC);
for (i = 0; i < DIMM_SOCKETS; i++) {
- value = spd_read_byte(DIMM_SPD_BASE + i, SPD_REFRESH);
+ value = spd_read_byte(DIMM0 + i, SPD_REFRESH);
if (value < 0)
continue;
reg = (reg & 0xf8) | refresh_rate_map[(value & 0x7f)];
@@ -750,7 +750,7 @@
for (i = 0; i < DIMM_SOCKETS; i++) {
unsigned int device;
- device = DIMM_SPD_BASE + i;
+ device = DIMM0 + i;
bpr >>= 2;
/* First check if a DIMM is actually present. */
diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h
index 18268a1..4bc0796 100644
--- a/src/northbridge/intel/i440bx/raminit.h
+++ b/src/northbridge/intel/i440bx/raminit.h
@@ -24,9 +24,6 @@
/* The 440BX supports up to four (single- or double-sided) DIMMs. */
#define DIMM_SOCKETS 4
-/* DIMMs 1-4 are at 0x50, 0x51, 0x52, 0x53. */
-#define DIMM_SPD_BASE 0x50
-
/* Function prototypes. */
int spd_read_byte(unsigned int device, unsigned int address);
void sdram_set_registers(void);
diff --git a/src/northbridge/intel/i440lx/raminit.c b/src/northbridge/intel/i440lx/raminit.c
index dcb2273..93fc102 100644
--- a/src/northbridge/intel/i440lx/raminit.c
+++ b/src/northbridge/intel/i440lx/raminit.c
@@ -301,18 +301,18 @@
PRINT_DEBUG("DIMM");
PRINT_DEBUG_HEX8(i);
PRINT_DEBUG(" rows: ");
- PRINT_DEBUG_HEX8(spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_DIMM_BANKS) & 0xFF);
+ PRINT_DEBUG_HEX8(spd_read_byte(DIMM0 + i, SPD_NUM_DIMM_BANKS) & 0xFF);
PRINT_DEBUG(" rowsize: ");
- PRINT_DEBUG_HEX8(spd_read_byte(DIMM_SPD_BASE + i, SPD_DENSITY_OF_EACH_ROW_ON_MODULE) & 0xFF);
+ PRINT_DEBUG_HEX8(spd_read_byte(DIMM0 + i, SPD_DENSITY_OF_EACH_ROW_ON_MODULE) & 0xFF);
PRINT_DEBUG(" modulesize: ");
- j = spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_DIMM_BANKS);
+ j = spd_read_byte(DIMM0 + i, SPD_NUM_DIMM_BANKS);
if (j < 0)
j = 0;
else
ds = j;
- j = spd_read_byte(DIMM_SPD_BASE + i, SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
+ j = spd_read_byte(DIMM0 + i, SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
if (j < 0)
j = 0;
diff --git a/src/northbridge/intel/i440lx/raminit.h b/src/northbridge/intel/i440lx/raminit.h
index 37331f4..8dcd02b 100644
--- a/src/northbridge/intel/i440lx/raminit.h
+++ b/src/northbridge/intel/i440lx/raminit.h
@@ -25,7 +25,4 @@
/* The 440LX supports up to four (single- or double-sided) DIMMs. */
#define DIMM_SOCKETS 4
-/* DIMMs 1-4 are at 0x50, 0x51, 0x52, 0x53. */
-#define DIMM_SPD_BASE 0x50
-
#endif /* RAMINIT_H */
diff --git a/src/northbridge/intel/i82810/debug.c b/src/northbridge/intel/i82810/debug.c
index 44ee197..16a9089 100644
--- a/src/northbridge/intel/i82810/debug.c
+++ b/src/northbridge/intel/i82810/debug.c
@@ -7,7 +7,7 @@
print_debug("\n");
for(i = 0; i < DIMM_SOCKETS; i++) {
unsigned device;
- device = DIMM_SPD_BASE + i;
+ device = DIMM0 + i;
if (device) {
int j;
print_debug("dimm: ");
diff --git a/src/northbridge/intel/i82810/raminit.c b/src/northbridge/intel/i82810/raminit.c
index 83b21b1..df2916e 100644
--- a/src/northbridge/intel/i82810/raminit.c
+++ b/src/northbridge/intel/i82810/raminit.c
@@ -255,12 +255,12 @@
for (i = 0; i < DIMM_SOCKETS; i++) {
/* First check if a DIMM is actually present. */
- if (smbus_read_byte(DIMM_SPD_BASE + i, 2) == 4) {
+ if (smbus_read_byte(DIMM0 + i, 2) == 4) {
print_debug("Found DIMM in slot ");
print_debug_hex8(i);
print_debug("\n");
- dimm_size = smbus_read_byte(DIMM_SPD_BASE + i, 31);
+ dimm_size = smbus_read_byte(DIMM0 + i, 31);
/* WISHLIST: would be nice to display it as decimal? */
print_debug("DIMM is 0x");
@@ -293,7 +293,7 @@
/* If the DIMM is dual-sided, the DRP value is +2 */
/* TODO: Figure out asymetrical configurations. */
- if ((smbus_read_byte(DIMM_SPD_BASE + i, 127) | 0xf) ==
+ if ((smbus_read_byte(DIMM0 + i, 127) | 0xf) ==
0xff) {
print_debug("DIMM is dual-sided\n");
dimm_size += 2;
@@ -361,20 +361,18 @@
/* Check first slot. */
d0.size = d0.ds = d0.ss = 0;
- if (smbus_read_byte(DIMM_SPD_BASE, SPD_MEMORY_TYPE)
- == SPD_MEMORY_TYPE_SDRAM) {
- d0.size = smbus_read_byte(DIMM_SPD_BASE, SPD_BANK_DENSITY);
- d0.ds = smbus_read_byte(DIMM_SPD_BASE, SPD_NUM_DIMM_BANKS) > 1;
+ if (smbus_read_byte(DIMM0, SPD_MEMORY_TYPE) == SPD_MEMORY_TYPE_SDRAM) {
+ d0.size = smbus_read_byte(DIMM0, SPD_BANK_DENSITY);
+ d0.ds = smbus_read_byte(DIMM0, SPD_NUM_DIMM_BANKS) > 1;
d0.ss = !d0.ds;
}
/* Check second slot. */
d1.size = d1.ds = d1.ss = 0;
- if (smbus_read_byte(DIMM_SPD_BASE + 1, SPD_MEMORY_TYPE)
+ if (smbus_read_byte(DIMM0 + 1, SPD_MEMORY_TYPE)
== SPD_MEMORY_TYPE_SDRAM) {
- d1.size = smbus_read_byte(DIMM_SPD_BASE + 1, SPD_BANK_DENSITY);
- d1.ds = smbus_read_byte(DIMM_SPD_BASE + 1,
- SPD_NUM_DIMM_BANKS) > 1;
+ d1.size = smbus_read_byte(DIMM0 + 1, SPD_BANK_DENSITY);
+ d1.ds = smbus_read_byte(DIMM0 + 1, SPD_NUM_DIMM_BANKS) > 1;
d1.ss = !d1.ds;
}
diff --git a/src/northbridge/intel/i82810/raminit.h b/src/northbridge/intel/i82810/raminit.h
index fbf6423..186589a 100644
--- a/src/northbridge/intel/i82810/raminit.h
+++ b/src/northbridge/intel/i82810/raminit.h
@@ -24,9 +24,6 @@
/* The 82810 supports max. 2 dual-sided DIMMs. */
#define DIMM_SOCKETS 2
-/* DIMM0 is at 0x50, DIMM1 is at 0x51. */
-#define DIMM_SPD_BASE 0x50
-
/* Function prototypes. */
void sdram_set_registers(void);
void sdram_set_spd_registers(void);
diff --git a/src/northbridge/intel/i82830/raminit.c b/src/northbridge/intel/i82830/raminit.c
index 8d75c42..f96306e 100644
--- a/src/northbridge/intel/i82830/raminit.c
+++ b/src/northbridge/intel/i82830/raminit.c
@@ -101,16 +101,16 @@
switch (row) {
case 0:
- device = DIMM_SPD_BASE;
+ device = DIMM0;
break;
case 1:
- device = DIMM_SPD_BASE;
+ device = DIMM0;
break;
case 2:
- device = DIMM_SPD_BASE + 1;
+ device = DIMM0 + 1;
break;
case 3:
- device = DIMM_SPD_BASE + 1;
+ device = DIMM0 + 1;
break;
}
@@ -224,7 +224,7 @@
for (i = 0; i < DIMM_SOCKETS; i++) {
struct dimm_size sz;
unsigned device;
- device = DIMM_SPD_BASE + i;
+ device = DIMM0 + i;
drb1 = 0;
drb2 = 0;
@@ -316,7 +316,7 @@
for (i = 0; i < DIMM_SOCKETS; i++) {
unsigned device;
- device = DIMM_SPD_BASE + i;
+ device = DIMM0 + i;
/* First check if a DIMM is actually present. */
if (spd_read_byte(device, SPD_MEMORY_TYPE) == 0x4) {
diff --git a/src/northbridge/intel/i82830/raminit.h b/src/northbridge/intel/i82830/raminit.h
index 3b4bf5f..f54409b 100644
--- a/src/northbridge/intel/i82830/raminit.h
+++ b/src/northbridge/intel/i82830/raminit.h
@@ -27,7 +27,4 @@
/* The 82830 supports max. 2 dual-sided SO-DIMMs. */
#define DIMM_SOCKETS 2
-/* DIMM0 is at 0x50, DIMM1 is at 0x51. */
-#define DIMM_SPD_BASE 0x50
-
#endif /* NORTHBRIDGE_INTEL_I82830_RAMINIT_H */
diff --git a/src/northbridge/intel/i855/raminit.h b/src/northbridge/intel/i855/raminit.h
index 1f1b34d..2ac0fde 100644
--- a/src/northbridge/intel/i855/raminit.h
+++ b/src/northbridge/intel/i855/raminit.h
@@ -28,9 +28,6 @@
/* The i855 supports max. 2 dual-sided SO-DIMMs. */
#define DIMM_SOCKETS 2
-/* DIMM0 is at 0x50, DIMM1 is at 0x51. */
-#define DIMM_SPD_BASE 0x50
-
struct mem_controller {
device_t d0;
uint16_t channel0[DIMM_SOCKETS];
@@ -38,5 +35,4 @@
void sdram_initialize(int controllers, const struct mem_controller *ctrl);
-
#endif /* NORTHBRIDGE_INTEL_I855_RAMINIT_H */
diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c
index 8dc76fe..859a1ef 100644
--- a/src/northbridge/intel/i945/debug.c
+++ b/src/northbridge/intel/i945/debug.c
@@ -19,6 +19,7 @@
* MA 02110-1301 USA
*/
+#include <spd.h>
#include <lib.h>
#include <arch/io.h>
#include <arch/romcc_io.h>
@@ -26,10 +27,6 @@
#include <console/console.h>
#include "i945.h"
-#define SMBUS_MEM_DEVICE_START 0x50
-#define SMBUS_MEM_DEVICE_END 0x53
-#define SMBUS_MEM_DEVICE_INC 1
-
void print_pci_devices(void)
{
device_t dev;
@@ -88,8 +85,8 @@
void dump_spd_registers(void)
{
unsigned device;
- device = SMBUS_MEM_DEVICE_START;
- while(device <= SMBUS_MEM_DEVICE_END) {
+ device = DIMM0;
+ while(device <= DIMM3) {
int status = 0;
int i;
printk(BIOS_DEBUG, "\ndimm %02x", device);
@@ -105,7 +102,7 @@
}
printk(BIOS_DEBUG, "%02x ", status);
}
- device += SMBUS_MEM_DEVICE_INC;
+ device++;
printk(BIOS_DEBUG, "\n");
}
}
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index c23fa64..77b9ade 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -323,15 +323,14 @@
/**
* i945 supports two DIMMs, in two configurations:
*
- * - single channel with two dimms
- * - dual channel with one dimm per channel
+ * - single channel with two DIMMs
+ * - dual channel with one DIMM per channel
*
- * In practice dual channel mainboards have their spd at 0x50, 0x52
- * whereas single channel configurations have their spd at 0x50/x51
+ * In practice dual channel mainboards have their SPD at 0x50/0x52
+ * whereas single channel configurations have their SPD at 0x50/0x51.
*
* The capability register knows a lot about the channel configuration
- * but for now we stick with the information we gather from the SPD
- * ROMs
+ * but for now we stick with the information we gather via SPD.
*/
if (sdram_capabilities_dual_channel()) {
@@ -362,7 +361,7 @@
*/
for (i=0; i<(2 * DIMM_SOCKETS); i++) {
- u8 reg8, device = DIMM_SPD_BASE + i;
+ u8 reg8, device = DIMM0 + i;
/* Initialize the socket information with a sane value */
sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED;
@@ -453,7 +452,7 @@
continue;
/* Is the current DIMM a stacked DIMM? */
- if (spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_DIMM_BANKS) & (1 << 4))
+ if (spd_read_byte(DIMM0 + i, SPD_NUM_DIMM_BANKS) & (1 << 4))
sysinfo->package = 1;
}
}
@@ -470,7 +469,7 @@
for (i=0; i<2*DIMM_SOCKETS; i++) {
if (sysinfo->dimm[i] != SYSINFO_DIMM_NOT_POPULATED)
- cas_mask &= spd_read_byte(DIMM_SPD_BASE + i, SPD_ACCEPTABLE_CAS_LATENCIES);
+ cas_mask &= spd_read_byte(DIMM0 + i, SPD_ACCEPTABLE_CAS_LATENCIES);
}
if(!cas_mask) {
@@ -531,7 +530,7 @@
continue;
}
- current_cas_mask = spd_read_byte(DIMM_SPD_BASE + i, SPD_ACCEPTABLE_CAS_LATENCIES);
+ current_cas_mask = spd_read_byte(DIMM0 + i, SPD_ACCEPTABLE_CAS_LATENCIES);
while (current_cas_mask) {
int highest_supported_cas = 0, current_cas = 0;
@@ -553,11 +552,11 @@
idx = highest_supported_cas - current_cas;
PRINTK_DEBUG("idx=%d, ", idx);
- PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[2*idx]));
- PRINTK_DEBUG("tAC=%x", spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[(2*idx)+1]));
+ PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(DIMM0 + i, spd_lookup_table[2*idx]));
+ PRINTK_DEBUG("tAC=%x", spd_read_byte(DIMM0 + i, spd_lookup_table[(2*idx)+1]));
- if (spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] &&
- spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) {
+ if (spd_read_byte(DIMM0 + i, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] &&
+ spd_read_byte(DIMM0 + i, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) {
PRINTK_DEBUG(": OK\n");
break;
}
@@ -621,7 +620,7 @@
if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
continue;
- reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
+ reg8 = spd_read_byte(DIMM0 + i, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
if (!reg8) {
die("Invalid tRAS value.\n");
}
@@ -661,7 +660,7 @@
if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
continue;
- reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_ROW_PRECHARGE_TIME);
+ reg8 = spd_read_byte(DIMM0 + i, SPD_MIN_ROW_PRECHARGE_TIME);
if (!reg8) {
die("Invalid tRP value.\n");
}
@@ -702,7 +701,7 @@
if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
continue;
- reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_RAS_TO_CAS_DELAY);
+ reg8 = spd_read_byte(DIMM0 + i, SPD_MIN_RAS_TO_CAS_DELAY);
if (!reg8) {
die("Invalid tRCD value.\n");
}
@@ -742,7 +741,7 @@
if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
continue;
- reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_WRITE_RECOVERY_TIME);
+ reg8 = spd_read_byte(DIMM0 + i, SPD_WRITE_RECOVERY_TIME);
if (!reg8) {
die("Invalid tWR value.\n");
}
@@ -823,7 +822,7 @@
if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
continue;
- refresh = spd_read_byte(DIMM_SPD_BASE + i, SPD_REFRESH) & ~(1 << 7);
+ refresh = spd_read_byte(DIMM0 + i, SPD_REFRESH) & ~(1 << 7);
/* 15.6us */
if (!refresh)
@@ -851,7 +850,7 @@
if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
continue;
- if (!(spd_read_byte(DIMM_SPD_BASE + i, SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8))
+ if (!(spd_read_byte(DIMM0 + i, SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8))
die("Only DDR-II RAM with burst length 8 is supported by this chipset.\n");
}
}
@@ -1471,9 +1470,9 @@
if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
continue;
- sz = sdram_get_dimm_size(DIMM_SPD_BASE + i);
+ sz = sdram_get_dimm_size(DIMM0 + i);
- sysinfo->banks[i] = spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_BANKS_PER_SDRAM); /* banks */
+ sysinfo->banks[i] = spd_read_byte(DIMM0 + i, SPD_NUM_BANKS_PER_SDRAM); /* banks */
if (sz.side1 < 30)
die("DDR-II rank size smaller than 128MB is not supported.\n");
@@ -1565,7 +1564,7 @@
continue;
}
- device = DIMM_SPD_BASE + i;
+ device = DIMM0 + i;
value = spd_read_byte(device, SPD_NUM_ROWS); /* rows */
columnsrows = (value & 0x0f);
diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h
index 026d715..197a600 100644
--- a/src/northbridge/intel/i945/raminit.h
+++ b/src/northbridge/intel/i945/raminit.h
@@ -22,7 +22,6 @@
#define DIMM_SOCKETS 2
-#define DIMM_SPD_BASE 0x50
#define DIMM_TCO_BASE 0x30
/* Burst length is always 8 */