commit | d74f6f5a5d0a95e4c3b499ae730ef98c7a8260cd | [log] [tgz] |
---|---|---|
author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | Thu Nov 04 12:03:50 2021 +0800 |
committer | Patrick Georgi <pgeorgi@google.com> | Fri Nov 05 12:57:25 2021 +0000 |
tree | 37a8d5395d4a9c173737c311991a1943549e43cd | |
parent | ba3af5e2ff3608f2be5e318e20d60686228a1c97 [diff] |
mb/google/brya/var/felwinter: Correct typeC EC mux port Type C port2 uses EC mux port0 as per schematics. BUG=b:204230406 TEST=No error message in depthahrge. update_port_state: port C2: get_usb_pd_mux_info failed Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I85218c81018b248c41a2cdaf9360a86e2a7d4d7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb index 0fa2e61..9bd7ab5 100644 --- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb +++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb
@@ -123,10 +123,9 @@ end end device ref pch_espi on - #TBD, felwinter remove typeC port0 chip ec/google/chromeec use conn1 as mux_conn[1] - use conn2 as mux_conn[2] + use conn2 as mux_conn[0] device pnp 0c09.0 on end end end