VIA C7 NANO: Fix early MTRR setting

It would not be possible to set MTRR for range 1MiB to 4MiB.
Our RAMTOP is power of 2 and enabling cache for bottom
1MiB should cause no problems.

Change-Id: I3619bc25be60f42b68615bfcdf36f02d66796e02
Signed-off-by: Kyösti Mälkki <>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <>
1 file changed