- Fix some copy bugs and thinkos in the i440bx SMbus
read code. SBbus reads to RAM now work. Yah!
- Rename the register constants to something I can look at
more easily.
- Make the logic flow match the flow from V1 assembly
- #if 0 out other SMbus functions that are still broken.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2353 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/src/southbridge/intel/i440bx/i440bx_early_smbus.c b/src/southbridge/intel/i440bx/i440bx_early_smbus.c
index a3db7b8..172414e 100644
--- a/src/southbridge/intel/i440bx/i440bx_early_smbus.c
+++ b/src/southbridge/intel/i440bx/i440bx_early_smbus.c
@@ -11,7 +11,7 @@
}
uint8_t enable;
print_spew("SMBus controller enabled\r\n");
- pci_write_config32(dev, 0x90, SMBUS_IO_BASE );
+ pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1 );
// Enable and set SMBBus
// 0x01 Interrupt to SMI#
// (0x4<<1)|1 set interrupt to IRQ9
@@ -21,7 +21,24 @@
pci_write_config16(dev, 0x04, 1);
/* clear any lingering errors, so the transaction will run */
- outb(0x1e, SMBUS_IO_BASE + SMBGSTATUS);
+ outb(0x1e, SMBUS_IO_BASE + SMBHST_STATUS);
+}
+
+
+
+static int smbus_read_byte(unsigned device, unsigned address)
+{
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
+}
+
+
+// The following functions are broken. Do no use until you
+// have fixed the low level code to do the right thing.
+//
+#if 0
+static int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
+{
+ return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);
}
static int smbus_recv_byte(unsigned device)
@@ -33,13 +50,4 @@
{
return do_smbus_send_byte(SMBUS_IO_BASE, device, val);
}
-
-static int smbus_read_byte(unsigned device, unsigned address)
-{
- return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
-}
-
-static int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
-{
- return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);
-}
+#endif