mainboards: Drop PWRS from GNVS
Initialize variable to 1 to indicate AC power supply.
If platform has EC it will set this correctly based on
whether plugged on the charger or not.
Change-Id: I3f834cf7563b9e512fcab34cdb7a27a9f0fd31c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49352
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/acpi/dsdt_top.asl b/src/acpi/dsdt_top.asl
index d2fcfa6..735389d 100644
--- a/src/acpi/dsdt_top.asl
+++ b/src/acpi/dsdt_top.asl
@@ -7,3 +7,6 @@
#include <vendorcode/google/chromeos/acpi/gnvs.asl>
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
#endif
+
+/* Power state (AC = 1) */
+Name (PWRS, One)
diff --git a/src/mainboard/acer/g43t-am3/acpi_tables.c b/src/mainboard/acer/g43t-am3/acpi_tables.c
index 67e7b1a..cd44ed2 100644
--- a/src/mainboard/acer/g43t-am3/acpi_tables.c
+++ b/src/mainboard/acer/g43t-am3/acpi_tables.c
@@ -5,6 +5,5 @@
void mainboard_fill_gnvs(struct global_nvs *gnvs)
{
- gnvs->pwrs = 1; /* Power state (AC = 1) */
gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */
}
diff --git a/src/mainboard/asrock/g41c-gs/acpi_tables.c b/src/mainboard/asrock/g41c-gs/acpi_tables.c
deleted file mode 100644
index 566cad7..0000000
--- a/src/mainboard/asrock/g41c-gs/acpi_tables.c
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <acpi/acpi_gnvs.h>
-#include <soc/nvs.h>
-
-void mainboard_fill_gnvs(struct global_nvs *gnvs)
-{
- gnvs->pwrs = 1; /* Power state (AC = 1) */
-}
diff --git a/src/mainboard/asus/p5qc/acpi_tables.c b/src/mainboard/asus/p5qc/acpi_tables.c
index 1ac0957..cd44ed2 100644
--- a/src/mainboard/asus/p5qc/acpi_tables.c
+++ b/src/mainboard/asus/p5qc/acpi_tables.c
@@ -5,6 +5,5 @@
void mainboard_fill_gnvs(struct global_nvs *gnvs)
{
- gnvs->pwrs = 1; /* Power state (AC = 1) */
gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */
}
diff --git a/src/mainboard/asus/p5ql-em/acpi_tables.c b/src/mainboard/asus/p5ql-em/acpi_tables.c
index 1ac0957..cd44ed2 100644
--- a/src/mainboard/asus/p5ql-em/acpi_tables.c
+++ b/src/mainboard/asus/p5ql-em/acpi_tables.c
@@ -5,6 +5,5 @@
void mainboard_fill_gnvs(struct global_nvs *gnvs)
{
- gnvs->pwrs = 1; /* Power state (AC = 1) */
gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */
}
diff --git a/src/mainboard/asus/p5qpl-am/acpi_tables.c b/src/mainboard/asus/p5qpl-am/acpi_tables.c
deleted file mode 100644
index 566cad7..0000000
--- a/src/mainboard/asus/p5qpl-am/acpi_tables.c
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <acpi/acpi_gnvs.h>
-#include <soc/nvs.h>
-
-void mainboard_fill_gnvs(struct global_nvs *gnvs)
-{
- gnvs->pwrs = 1; /* Power state (AC = 1) */
-}
diff --git a/src/mainboard/foxconn/g41s-k/acpi_tables.c b/src/mainboard/foxconn/g41s-k/acpi_tables.c
deleted file mode 100644
index 3bdb266..0000000
--- a/src/mainboard/foxconn/g41s-k/acpi_tables.c
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <acpi/acpi_gnvs.h>
-#include <soc/nvs.h>
-
-void mainboard_fill_gnvs(struct global_nvs *gnvs)
-{
- gnvs->pwrs = 1; /* Power state (AC = 1) */
-}
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c b/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c
index 1ac0957..cd44ed2 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c
@@ -5,6 +5,5 @@
void mainboard_fill_gnvs(struct global_nvs *gnvs)
{
- gnvs->pwrs = 1; /* Power state (AC = 1) */
gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */
}
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl
index 6986864..465c77c 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl
+++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl
@@ -16,10 +16,6 @@
Name(OSV, Ones) /* Assume nothing */
Name(PICM, One) /* Assume APIC */
- /* Variables used by EC */
- /* TODO: These may belong in global non-volatile storage */
- Name(PWRS, Zero)
-
/* AcpiGpe0Blk */
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)
Field(GP0B, ByteAcc, NoLock, Preserve) {
diff --git a/src/mainboard/intel/dg41wv/acpi_tables.c b/src/mainboard/intel/dg41wv/acpi_tables.c
deleted file mode 100644
index 566cad7..0000000
--- a/src/mainboard/intel/dg41wv/acpi_tables.c
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <acpi/acpi_gnvs.h>
-#include <soc/nvs.h>
-
-void mainboard_fill_gnvs(struct global_nvs *gnvs)
-{
- gnvs->pwrs = 1; /* Power state (AC = 1) */
-}
diff --git a/src/mainboard/intel/dg43gt/acpi_tables.c b/src/mainboard/intel/dg43gt/acpi_tables.c
index 1ac0957..cd44ed2 100644
--- a/src/mainboard/intel/dg43gt/acpi_tables.c
+++ b/src/mainboard/intel/dg43gt/acpi_tables.c
@@ -5,6 +5,5 @@
void mainboard_fill_gnvs(struct global_nvs *gnvs)
{
- gnvs->pwrs = 1; /* Power state (AC = 1) */
gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */
}
diff --git a/src/mainboard/lenovo/g505s/acpi/mainboard.asl b/src/mainboard/lenovo/g505s/acpi/mainboard.asl
index 6986864..465c77c 100644
--- a/src/mainboard/lenovo/g505s/acpi/mainboard.asl
+++ b/src/mainboard/lenovo/g505s/acpi/mainboard.asl
@@ -16,10 +16,6 @@
Name(OSV, Ones) /* Assume nothing */
Name(PICM, One) /* Assume APIC */
- /* Variables used by EC */
- /* TODO: These may belong in global non-volatile storage */
- Name(PWRS, Zero)
-
/* AcpiGpe0Blk */
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)
Field(GP0B, ByteAcc, NoLock, Preserve) {
diff --git a/src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c b/src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c
deleted file mode 100644
index 566cad7..0000000
--- a/src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <acpi/acpi_gnvs.h>
-#include <soc/nvs.h>
-
-void mainboard_fill_gnvs(struct global_nvs *gnvs)
-{
- gnvs->pwrs = 1; /* Power state (AC = 1) */
-}
diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl
index 31d375c..3f02657 100644
--- a/src/soc/amd/picasso/acpi/globalnvs.asl
+++ b/src/soc/amd/picasso/acpi/globalnvs.asl
@@ -14,7 +14,7 @@
/* Miscellaneous */
, 8, // 0x00 - Processor Count
LIDS, 8, // 0x01 - LID State
- PWRS, 8, // 0x02 - AC Power State
+ , 8, // 0x02 - AC Power State
CBMC, 32, // 0x03 - 0x06 - coreboot Memory Console
PM1I, 64, // 0x07 - 0x0e - System Wake Source - PM1 Index
GPEI, 64, // 0x0f - 0x16 - GPE Wake Source
diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h
index b8945ff..2829f7d 100644
--- a/src/soc/amd/picasso/include/soc/nvs.h
+++ b/src/soc/amd/picasso/include/soc/nvs.h
@@ -16,7 +16,7 @@
/* Miscellaneous */
uint8_t unused_was_pcnt; /* 0x00 - Processor Count */
uint8_t lids; /* 0x01 - LID State */
- uint8_t pwrs; /* 0x02 - AC Power State */
+ uint8_t unused_was_pwrs; /* 0x02 - AC Power State */
uint32_t cbmc; /* 0x03 - 0x06 - coreboot Memory Console */
uint64_t pm1i; /* 0x07 - 0x0e - System Wake Source - PM1 Index */
uint64_t gpei; /* 0x0f - 0x16 - GPE Wake Source */
diff --git a/src/soc/amd/stoneyridge/acpi/globalnvs.asl b/src/soc/amd/stoneyridge/acpi/globalnvs.asl
index ce3653c..e60789e 100644
--- a/src/soc/amd/stoneyridge/acpi/globalnvs.asl
+++ b/src/soc/amd/stoneyridge/acpi/globalnvs.asl
@@ -11,7 +11,7 @@
/* Miscellaneous */
, 8, // 0x00 - Processor Count
LIDS, 8, // 0x01 - LID State
- PWRS, 8, // 0x02 - AC Power State
+ , 8, // 0x02 - AC Power State
CBMC, 32, // 0x03 - 0x06 - coreboot Memory Console
PM1I, 64, // 0x07 - 0x0e - System Wake Source - PM1 Index
GPEI, 64, // 0x0f - 0x16 - GPE Wake Source
diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h
index 055d74b..2b61c77 100644
--- a/src/soc/amd/stoneyridge/include/soc/nvs.h
+++ b/src/soc/amd/stoneyridge/include/soc/nvs.h
@@ -16,7 +16,7 @@
/* Miscellaneous */
uint8_t unused_was_pcnt; /* 0x00 - Processor Count */
uint8_t lids; /* 0x01 - LID State */
- uint8_t pwrs; /* 0x02 - AC Power State */
+ uint8_t unused_was_pwrs; /* 0x02 - AC Power State */
uint32_t cbmc; /* 0x03 - 0x06 - coreboot Memory Console */
uint64_t pm1i; /* 0x07 - 0x0e - System Wake Source - PM1 Index */
uint64_t gpei; /* 0x0f - 0x16 - GPE Wake Source */
diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl
index b79a446..225e9db 100644
--- a/src/soc/intel/apollolake/acpi/globalnvs.asl
+++ b/src/soc/intel/apollolake/acpi/globalnvs.asl
@@ -12,7 +12,7 @@
, 8, // 0x00 - Processor Count
PPCM, 8, // 0x01 - Max PPC State
LIDS, 8, // 0x02 - LID State
- PWRS, 8, // 0x03 - AC Power State
+ , 8, // 0x03 - AC Power State
DPTE, 8, // 0x04 - Enable DPTF
CBMC, 32, // 0x05 - 0x08 - coreboot Memory Console
PM1I, 64, // 0x09 - 0x10 - System Wake Source - PM1 Index
diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h
index 1f2b8ad..aa909a8 100644
--- a/src/soc/intel/apollolake/include/soc/nvs.h
+++ b/src/soc/intel/apollolake/include/soc/nvs.h
@@ -16,7 +16,7 @@
uint8_t unused_was_pcnt; /* 0x00 - Processor Count */
uint8_t ppcm; /* 0x01 - Max PPC State */
uint8_t lids; /* 0x02 - LID State */
- uint8_t pwrs; /* 0x03 - AC Power State */
+ uint8_t unused_was_pwrs; /* 0x03 - AC Power State */
uint8_t dpte; /* 0x04 - Enable DPTF */
uint32_t cbmc; /* 0x05 - 0x08 - coreboot Memory Console */
uint64_t pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */
diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl
index c73b7a7..20b7ed4 100644
--- a/src/soc/intel/baytrail/acpi/globalnvs.asl
+++ b/src/soc/intel/baytrail/acpi/globalnvs.asl
@@ -19,7 +19,7 @@
PRM5, 8, /* 0x0a - Lock function parameter */
P80D, 32, /* 0x0b - Debug port (IO 0x80) value */
LIDS, 8, /* 0x0f - LID state (open = 1) */
- PWRS, 8, /* 0x10 - Power State (AC = 1) */
+ , 8, /* 0x10 - Power State (AC = 1) */
, 8, /* 0x11 - Processor count */
TPMP, 8, /* 0x12 - TPM Present and Enabled */
TLVL, 8, /* 0x13 - Throttle Level */
diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h
index a068d1e..d6136de 100644
--- a/src/soc/intel/baytrail/include/soc/nvs.h
+++ b/src/soc/intel/baytrail/include/soc/nvs.h
@@ -19,7 +19,7 @@
u8 prm5; /* 0x0a - Lock function parameter */
u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
u8 lids; /* 0x0f - LID state (open = 1) */
- u8 pwrs; /* 0x10 - Power state (AC = 1) */
+ u8 unused_was_pwrs; /* 0x10 - Power state (AC = 1) */
u8 unused_was_pcnt; /* 0x11 - Processor Count */
u8 tpmp; /* 0x12 - TPM Present and Enabled */
u8 tlvl; /* 0x13 - Throttle Level */
diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl
index 9a43671..d13e4a4 100644
--- a/src/soc/intel/braswell/acpi/globalnvs.asl
+++ b/src/soc/intel/braswell/acpi/globalnvs.asl
@@ -19,7 +19,7 @@
PRM5, 8, /* 0x0a - Lock function parameter */
P80D, 32, /* 0x0b - Debug port (IO 0x80) value */
LIDS, 8, /* 0x0f - LID state (open = 1) */
- PWRS, 8, /* 0x10 - Power State (AC = 1) */
+ , 8, /* 0x10 - Power State (AC = 1) */
, 8, /* 0x11 - Processor count */
TPMP, 8, /* 0x12 - TPM Present and Enabled */
TLVL, 8, /* 0x13 - Throttle Level */
diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h
index 7d27c3f..82ed4f5 100644
--- a/src/soc/intel/braswell/include/soc/nvs.h
+++ b/src/soc/intel/braswell/include/soc/nvs.h
@@ -19,7 +19,7 @@
u8 prm5; /* 0x0a - Lock function parameter */
u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
u8 lids; /* 0x0f - LID state (open = 1) */
- u8 pwrs; /* 0x10 - Power state (AC = 1) */
+ u8 unused_was_pwrs; /* 0x10 - Power state (AC = 1) */
u8 unused_was_pcnt; /* 0x11 - Processor Count */
u8 tpmp; /* 0x12 - TPM Present and Enabled */
u8 tlvl; /* 0x13 - Throttle Level */
diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h
index 70f26e8..1f9ae04 100644
--- a/src/soc/intel/broadwell/include/soc/nvs.h
+++ b/src/soc/intel/broadwell/include/soc/nvs.h
@@ -29,7 +29,7 @@
u8 s3u0; /* 0x14 - Enable USB in S3 */
u8 s33g; /* 0x15 - Enable 3G in S3 */
u8 lids; /* 0x16 - LID State */
- u8 pwrs; /* 0x17 - AC Power State */
+ u8 unused_was_pwrs; /* 0x17 - AC Power State */
u32 obsolete_cmem; /* 0x18 - 0x1b - CBMEM TOC */
u32 cbmc; /* 0x1c - 0x1f - coreboot Memory Console */
u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */
diff --git a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl
index 8a6bf87..876ac89 100644
--- a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl
+++ b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl
@@ -29,7 +29,7 @@
S3U0, 8, // 0x14 - Enable USB in S3
S33G, 8, // 0x15 - Enable 3G in S3
LIDS, 8, // 0x16 - LID State
- PWRS, 8, // 0x17 - AC Power State
+ , 8, // 0x17 - AC Power State
, 32, // 0x18 - 0x1b - CBMEM TOC
CBMC, 32, // 0x1c - 0x1f - coreboot Memory Console
PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit
diff --git a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
index d9ecfb3..1290fb0 100644
--- a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
+++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
@@ -13,7 +13,7 @@
PPCM, 8, // 0x04 - Max PPC State
TLVL, 8, // 0x05 - Throttle Level Limit
LIDS, 8, // 0x06 - LID State
- PWRS, 8, // 0x07 - AC Power State
+ , 8, // 0x07 - AC Power State
CBMC, 32, // 0x08 - 0x0b AC Power State
PM1I, 64, // 0x0c - 0x13 PM1 wake status bit
GPEI, 64, // 0x14 - 0x17 GPE wake status bit
diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h
index cba60f6..1bbd4c1 100644
--- a/src/soc/intel/common/block/include/intelblocks/nvs.h
+++ b/src/soc/intel/common/block/include/intelblocks/nvs.h
@@ -13,7 +13,7 @@
u8 ppcm; /* 0x04 - Max PPC State */
u8 tlvl; /* 0x05 - Throttle Level Limit */
u8 lids; /* 0x06 - LID State */
- u8 pwrs; /* 0x07 - AC Power State */
+ u8 unused_was_pwrs; /* 0x07 - AC Power State */
u32 cbmc; /* 0x08 - 0xb coreboot Memory Console */
u64 pm1i; /* 0x0c - 0x13 PM1 wake status bit */
u64 gpei; /* 0x14 - 0x1b GPE wake status bit */
diff --git a/src/soc/intel/denverton_ns/acpi/globalnvs.asl b/src/soc/intel/denverton_ns/acpi/globalnvs.asl
index 103397c..5bf706d 100644
--- a/src/soc/intel/denverton_ns/acpi/globalnvs.asl
+++ b/src/soc/intel/denverton_ns/acpi/globalnvs.asl
@@ -19,7 +19,7 @@
PRM5, 8, // 0x0a - Lock function parameter
P80D, 32, // 0x0b - Debug port (IO 0x80) value
LIDS, 8, // 0x0f - LID state (open = 1)
- PWRS, 8, // 0x10 - Power State (AC = 1)
+ , 8, // 0x10 - Power State (AC = 1)
, 8, // 0x11 - Processor count
TPMP, 8, // 0x12 - TPM Present and Enabled
TLVL, 8, // 0x13 - Throttle Level
diff --git a/src/soc/intel/denverton_ns/include/soc/nvs.h b/src/soc/intel/denverton_ns/include/soc/nvs.h
index 3dd747d..2191557 100644
--- a/src/soc/intel/denverton_ns/include/soc/nvs.h
+++ b/src/soc/intel/denverton_ns/include/soc/nvs.h
@@ -17,7 +17,7 @@
u8 prm5; /* 0x0a - Lock function parameter */
u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
u8 lids; /* 0x0f - LID state (open = 1) */
- u8 pwrs; /* 0x10 - Power state (AC = 1) */
+ u8 unused_was_pwrs; /* 0x10 - Power state (AC = 1) */
u8 unused_was_pcnt; /* 0x11 - Processor Count */
u8 tpmp; /* 0x12 - TPM Present and Enabled */
u8 tlvl; /* 0x13 - Throttle Level */
diff --git a/src/soc/intel/quark/include/soc/nvs.h b/src/soc/intel/quark/include/soc/nvs.h
index 64378cc..9974d5b 100644
--- a/src/soc/intel/quark/include/soc/nvs.h
+++ b/src/soc/intel/quark/include/soc/nvs.h
@@ -7,7 +7,7 @@
struct __packed global_nvs {
uint32_t cbmc; /* 0x00 - 0x03 - coreboot Memory Console */
- uint8_t pwrs; /* 0x4 - Power state (AC = 1) */
+ uint8_t unused_was_pwrs; /* 0x4 - Power state (AC = 1) */
/* Required for future unified acpi_save_wake_source. */
uint32_t pm1i;
diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl
index 97a69d5..1bb27eb 100644
--- a/src/soc/intel/skylake/acpi/globalnvs.asl
+++ b/src/soc/intel/skylake/acpi/globalnvs.asl
@@ -29,7 +29,7 @@
S3U0, 8, // 0x14 - Enable USB in S3
S33G, 8, // 0x15 - Enable 3G in S3
LIDS, 8, // 0x16 - LID State
- PWRS, 8, // 0x17 - AC Power State
+ , 8, // 0x17 - AC Power State
, 32, // 0x18 - 0x1b - CBMEM TOC
CBMC, 32, // 0x1c - 0x1f - coreboot Memory Console
PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit
diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h
index 2141518..e04364a 100644
--- a/src/soc/intel/skylake/include/soc/nvs.h
+++ b/src/soc/intel/skylake/include/soc/nvs.h
@@ -29,7 +29,7 @@
u8 s3u0; /* 0x14 - Enable USB in S3 */
u8 s33g; /* 0x15 - Enable 3G in S3 */
u8 lids; /* 0x16 - LID State */
- u8 pwrs; /* 0x17 - AC Power State */
+ u8 unused_was_pwrs; /* 0x17 - AC Power State */
u32 obsolete_cmem; /* 0x18 - 0x1b - CBMEM TOC */
u32 cbmc; /* 0x1c - 0x1f - coreboot Memory Console */
u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */
diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
index 20e32ef..0d798b8 100644
--- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
@@ -19,7 +19,7 @@
PRM5, 8, // 0x0a - Lock function parameter
P80D, 32, // 0x0b - Debug port (IO 0x80) value
LIDS, 8, // 0x0f - LID state (open = 1)
- PWRS, 8, // 0x10 - Power State (AC = 1)
+ , 8, // 0x10 - Power State (AC = 1)
/* Thermal policy */
Offset (0x11),
TLVL, 8, // 0x11 - Throttle Level Limit
diff --git a/src/southbridge/intel/bd82x6x/include/soc/nvs.h b/src/southbridge/intel/bd82x6x/include/soc/nvs.h
index 1c33b0c..95bf91b 100644
--- a/src/southbridge/intel/bd82x6x/include/soc/nvs.h
+++ b/src/southbridge/intel/bd82x6x/include/soc/nvs.h
@@ -19,7 +19,7 @@
u8 prm5; /* 0x0a - Lock function parameter */
u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
u8 lids; /* 0x0f - LID state (open = 1) */
- u8 pwrs; /* 0x10 - Power state (AC = 1) */
+ u8 unused_was_pwrs; /* 0x10 - Power state (AC = 1) */
/* Thermal policy */
u8 tlvl; /* 0x11 - Throttle Level Limit */
u8 flvl; /* 0x12 - Current FAN Level */
diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl
index a3b15b6..a1706a7 100644
--- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl
+++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl
@@ -19,7 +19,7 @@
PRM5, 8, // 0x0a - Lock function parameter
P80D, 32, // 0x0b - Debug port (IO 0x80) value
LIDS, 8, // 0x0f - LID state (open = 1)
- PWRS, 8, // 0x10 - Power State (AC = 1)
+ , 8, // 0x10 - Power State (AC = 1)
DBGS, 8, // 0x11 - Debug State
LINX, 8, // 0x12 - Linux OS
DCKN, 8, // 0x13 - PCIe docking state
diff --git a/src/southbridge/intel/i82801gx/include/soc/nvs.h b/src/southbridge/intel/i82801gx/include/soc/nvs.h
index 933921c..93272dc 100644
--- a/src/southbridge/intel/i82801gx/include/soc/nvs.h
+++ b/src/southbridge/intel/i82801gx/include/soc/nvs.h
@@ -19,7 +19,7 @@
u8 prm5; /* 0x0a - Lock function parameter */
u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
u8 lids; /* 0x0f - LID state (open = 1) */
- u8 pwrs; /* 0x10 - Power state (AC = 1) */
+ u8 unused_was_pwrs; /* 0x10 - Power state (AC = 1) */
u8 dbgs; /* 0x11 - Debug state */
u8 linx; /* 0x12 - Linux OS */
u8 dckn; /* 0x13 - PCIe docking state */
diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl
index f408a8c..55a368e 100644
--- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl
+++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl
@@ -19,7 +19,7 @@
PRM5, 8, // 0x0a - Lock function parameter
P80D, 32, // 0x0b - Debug port (IO 0x80) value
LIDS, 8, // 0x0f - LID state (open = 1)
- PWRS, 8, // 0x10 - Power State (AC = 1)
+ , 8, // 0x10 - Power State (AC = 1)
DBGS, 8, // 0x11 - Debug State
LINX, 8, // 0x12 - Linux OS
DCKN, 8, // 0x13 - PCIe docking state
diff --git a/src/southbridge/intel/i82801ix/include/soc/nvs.h b/src/southbridge/intel/i82801ix/include/soc/nvs.h
index 3c9aac9..5ae7f25 100644
--- a/src/southbridge/intel/i82801ix/include/soc/nvs.h
+++ b/src/southbridge/intel/i82801ix/include/soc/nvs.h
@@ -19,7 +19,7 @@
u8 prm5; /* 0x0a - Lock function parameter */
u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
u8 lids; /* 0x0f - LID state (open = 1) */
- u8 pwrs; /* 0x10 - Power state (AC = 1) */
+ u8 unused_was_pwrs; /* 0x10 - Power state (AC = 1) */
u8 dbgs; /* 0x11 - Debug state */
u8 linx; /* 0x12 - Linux OS */
u8 dckn; /* 0x13 - PCIe docking state */
diff --git a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl
index 264b52a..2b3e21b 100644
--- a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl
+++ b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl
@@ -19,7 +19,7 @@
PRM5, 8, // 0x0a - Lock function parameter
P80D, 32, // 0x0b - Debug port (IO 0x80) value
LIDS, 8, // 0x0f - LID state (open = 1)
- PWRS, 8, // 0x10 - Power State (AC = 1)
+ , 8, // 0x10 - Power State (AC = 1)
DBGS, 8, // 0x11 - Debug State
LINX, 8, // 0x12 - Linux OS
DCKN, 8, // 0x13 - PCIe docking state
diff --git a/src/southbridge/intel/i82801jx/include/soc/nvs.h b/src/southbridge/intel/i82801jx/include/soc/nvs.h
index 54c4a2c..96c5588 100644
--- a/src/southbridge/intel/i82801jx/include/soc/nvs.h
+++ b/src/southbridge/intel/i82801jx/include/soc/nvs.h
@@ -18,7 +18,7 @@
u8 prm5; /* 0x0a - Lock function parameter */
u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
u8 lids; /* 0x0f - LID state (open = 1) */
- u8 pwrs; /* 0x10 - Power state (AC = 1) */
+ u8 unused_was_pwrs; /* 0x10 - Power state (AC = 1) */
u8 dbgs; /* 0x11 - Debug state */
u8 linx; /* 0x12 - Linux OS */
u8 dckn; /* 0x13 - PCIe docking state */
diff --git a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl
index 46c6f4f..8525633e 100644
--- a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl
+++ b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl
@@ -19,7 +19,7 @@
PRM5, 8, // 0x0a - Lock function parameter
P80D, 32, // 0x0b - Debug port (IO 0x80) value
LIDS, 8, // 0x0f - LID state (open = 1)
- PWRS, 8, // 0x10 - Power State (AC = 1)
+ , 8, // 0x10 - Power State (AC = 1)
/* Thermal policy */
Offset (0x11),
TLVL, 8, // 0x11 - Throttle Level Limit
diff --git a/src/southbridge/intel/ibexpeak/include/soc/nvs.h b/src/southbridge/intel/ibexpeak/include/soc/nvs.h
index 03897cd..f552a02 100644
--- a/src/southbridge/intel/ibexpeak/include/soc/nvs.h
+++ b/src/southbridge/intel/ibexpeak/include/soc/nvs.h
@@ -20,7 +20,7 @@
u8 prm5; /* 0x0a - Lock function parameter */
u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
u8 lids; /* 0x0f - LID state (open = 1) */
- u8 pwrs; /* 0x10 - Power state (AC = 1) */
+ u8 unused_was_pwrs; /* 0x10 - Power state (AC = 1) */
/* Thermal policy */
u8 tlvl; /* 0x11 - Throttle Level Limit */
u8 flvl; /* 0x12 - Current FAN Level */
diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
index 1b06beb..d0c08a1 100644
--- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
@@ -19,7 +19,7 @@
PRM5, 8, // 0x0a - Lock function parameter
P80D, 32, // 0x0b - Debug port (IO 0x80) value
LIDS, 8, // 0x0f - LID state (open = 1)
- PWRS, 8, // 0x10 - Power State (AC = 1)
+ , 8, // 0x10 - Power State (AC = 1)
/* Thermal policy */
Offset (0x11),
TLVL, 8, // 0x11 - Throttle Level Limit
diff --git a/src/southbridge/intel/lynxpoint/include/soc/nvs.h b/src/southbridge/intel/lynxpoint/include/soc/nvs.h
index 7db206e..5bda60d 100644
--- a/src/southbridge/intel/lynxpoint/include/soc/nvs.h
+++ b/src/southbridge/intel/lynxpoint/include/soc/nvs.h
@@ -19,7 +19,7 @@
u8 prm5; /* 0x0a - Lock function parameter */
u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
u8 lids; /* 0x0f - LID state (open = 1) */
- u8 pwrs; /* 0x10 - Power state (AC = 1) */
+ u8 unused_was_pwrs; /* 0x10 - Power state (AC = 1) */
/* Thermal policy */
u8 tlvl; /* 0x11 - Throttle Level Limit */
u8 flvl; /* 0x12 - Current FAN Level */