soc/intel: Replace config_of_path() with config_of_soc()
The previously provided device path made no difference, all
integrated PCI devices point back to the same chip_info
structure.
Change reduces the exposure of various SA_DEVFN_xx and
PCH_DEVFN_xx from (ugly) soc/pci_devs.h.
Change-Id: Ibf13645fdd3ef7fd3d5c8217bb24d7ede045c790
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index d67b502..de37341 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -172,7 +172,7 @@
static void acpi_create_gnvs(global_nvs_t *gnvs)
{
- const struct soc_intel_skylake_config *config = config_of_path(PCH_DEVFN_LPC);
+ const struct soc_intel_skylake_config *config = config_of_soc();
/* Set unknown wake source */
gnvs->pm1i = -1;
@@ -232,7 +232,7 @@
void acpi_fill_fadt(acpi_fadt_t *fadt)
{
const uint16_t pmbase = ACPI_BASE_ADDRESS;
- config_t *config = config_of_path(SA_DEVFN_ROOT);
+ config_t *config = config_of_soc();
/* Use ACPI 3.0 revision */
fadt->header.revision = get_acpi_table_revision(FADT);
@@ -503,7 +503,7 @@
int totalcores = dev_count_cpu();
int cores_per_package = get_cores_per_package();
int numcpus = totalcores/cores_per_package;
- config_t *config = config_of_path(SA_DEVFN_ROOT);
+ config_t *config = config_of_soc();
int is_s0ix_enable = config->s0ix_enable;
printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
@@ -674,7 +674,7 @@
/* Save wake source information for calculating ACPI _SWS values */
int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0)
{
- const struct soc_intel_skylake_config *config = config_of_path(PCH_DEVFN_LPC);
+ const struct soc_intel_skylake_config *config = config_of_soc();
struct chipset_power_state *ps;
static uint32_t gpe0_sts[GPE0_REG_MAX];
uint32_t pm1_en;
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 462285c2..55fedd3 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -237,7 +237,7 @@
uintptr_t vbt_data = (uintptr_t)vbt_get();
int i;
- config = config_of_path(SA_DEVFN_ROOT);
+ config = config_of_soc();
mainboard_silicon_init_params(params);
/* Set PsysPmax if it is available from DT */
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 0d49d28..5424c91c 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -117,7 +117,7 @@
unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1;
u8 power_limit_1_val;
- config_t *conf = config_of_path(SA_DEVFN_ROOT);
+ config_t *conf = config_of_soc();
if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr))
power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1;
@@ -240,7 +240,7 @@
static void configure_thermal_target(void)
{
- config_t *conf = config_of_path(SA_DEVFN_ROOT);
+ config_t *conf = config_of_soc();
msr_t msr;
@@ -260,7 +260,7 @@
static void configure_isst(void)
{
- config_t *conf = config_of_path(SA_DEVFN_ROOT);
+ config_t *conf = config_of_soc();
msr_t msr;
@@ -286,7 +286,7 @@
static void configure_misc(void)
{
- config_t *conf = config_of_path(SA_DEVFN_ROOT);
+ config_t *conf = config_of_soc();
msr_t msr;
@@ -562,7 +562,7 @@
int soc_fill_sgx_param(struct sgx_param *sgx_param)
{
- config_t *conf = config_of_path(SA_DEVFN_ROOT);
+ config_t *conf = config_of_soc();
sgx_param->enable = conf->sgx_enable;
return 0;
diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c
index ffe0605..ab9297f 100644
--- a/src/soc/intel/skylake/pmc.c
+++ b/src/soc/intel/skylake/pmc.c
@@ -188,7 +188,7 @@
*/
static void pm1_handle_wake_pin(void *unused)
{
- const config_t *conf = config_of_path(SA_DEVFN_ROOT);
+ const config_t *conf = config_of_soc();
/* If WAKE# pin is enabled, bail out early. */
if (conf->deep_sx_config & DSX_EN_WAKE_PIN)
diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c
index 90f1b03..329cea9 100644
--- a/src/soc/intel/skylake/pmutil.c
+++ b/src/soc/intel/skylake/pmutil.c
@@ -177,7 +177,7 @@
{
DEVTREE_CONST struct soc_intel_skylake_config *config;
- config = config_of_path(PCH_DEVFN_PMC);
+ config = config_of_soc();
/* Assign to out variable */
*dw0 = config->gpe0_dw0;
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index a8bbfb6..f354af3 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -43,7 +43,7 @@
/* Program MCHBAR and DMIBAR */
systemagent_early_init();
- config = config_of_path(PCH_DEVFN_LPC);
+ config = config_of_soc();
/* Force a full memory train if RMT is enabled */
params->disable_saved_data = config->Rmt;
@@ -57,7 +57,7 @@
/* Set the parameters for MemoryInit */
- config = config_of_path(PCH_DEVFN_LPC);
+ config = config_of_soc();
/*
* Set IGD stolen size to 64MB. The FBC hardware for skylake does not
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index deda533..af89441 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -289,7 +289,7 @@
FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig;
- config = config_of_path(PCH_DEVFN_LPC);
+ config = config_of_soc();
soc_memory_init_params(m_cfg, config);
soc_peg_init_params(m_cfg, m_t_cfg, config);
diff --git a/src/soc/intel/skylake/romstage/systemagent.c b/src/soc/intel/skylake/romstage/systemagent.c
index 9b7ea24..bf0d506 100644
--- a/src/soc/intel/skylake/romstage/systemagent.c
+++ b/src/soc/intel/skylake/romstage/systemagent.c
@@ -29,7 +29,7 @@
const struct device *const igd_dev = pcidev_path_on_root(SA_DEVFN_IGD);
const struct soc_intel_skylake_config *config = NULL;
- config = config_of_path(SA_DEVFN_ROOT);
+ config = config_of_soc();
if (config->ignore_vtd)
return;