tree c4b6864ccbc50ef48a3b496f239b24f74b37e64d
parent 67d169721ade4e4d9ca827a4817894522696b5de
author Shankar, Vaibhav <vaibhav.shankar@intel.com> 1468868854 -0700
committer Aaron Durbin <adurbin@chromium.org> 1470156015 +0200

intel/amenia: Add GPIO changes to assert SLP_S0/Reset signal

PMIC/PMU: Set the iosstates for PMIC to assert the reset
signal, PMU to assert SLP_S0 signal.

Change-Id: Iec2dd659ea21f07d0bfe74194756786375cf775c
Signed-off-by: Shankar, Vaibhav <vaibhav.shankar@intel.com>
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/15777
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>