intel/smm/gen1: Use smm_subregion()
Change-Id: I371ed41f485b3143e47f091681198d6674928897
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34740
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c
index 6e2f703..7479a78 100644
--- a/src/northbridge/intel/gm45/memmap.c
+++ b/src/northbridge/intel/gm45/memmap.c
@@ -23,9 +23,9 @@
#include <device/pci_def.h>
#include <console/console.h>
#include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
#include <cbmem.h>
#include <program_loading.h>
-#include <stage_cache.h>
#include <cpu/intel/smm_reloc.h>
#include "gm45.h"
@@ -84,7 +84,7 @@
}
}
-u32 northbridge_get_tseg_base(void)
+static uintptr_t northbridge_get_tseg_base(void)
{
const pci_devfn_t dev = PCI_DEV(0, 0, 0);
@@ -107,7 +107,7 @@
return tor;
}
-u32 northbridge_get_tseg_size(void)
+static size_t northbridge_get_tseg_size(void)
{
const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC);
return decode_tseg_size(esmramc) << 10;
@@ -123,14 +123,10 @@
return (void *) top_of_ram;
}
-void stage_cache_external_region(void **base, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
{
- /* The stage cache lives at the end of the TSEG region.
- * The top of RAM is defined to be the TSEG base address.
- */
- *size = CONFIG_SMM_RESERVED_SIZE;
- *base = (void *)((uintptr_t)northbridge_get_tseg_base()
- + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
+ *start = northbridge_get_tseg_base();
+ *size = northbridge_get_tseg_size();
}
void fill_postcar_frame(struct postcar_frame *pcf)
diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c
index 8179f17..8207d06 100644
--- a/src/northbridge/intel/i945/memmap.c
+++ b/src/northbridge/intel/i945/memmap.c
@@ -22,10 +22,10 @@
#include "i945.h"
#include <console/console.h>
#include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
#include <program_loading.h>
#include <cpu/intel/smm_reloc.h>
#include <stdint.h>
-#include <stage_cache.h>
/* Decodes TSEG region size to bytes. */
u32 decode_tseg_size(const u8 esmramc)
@@ -45,7 +45,7 @@
}
}
-u32 northbridge_get_tseg_base(void)
+static uintptr_t northbridge_get_tseg_base(void)
{
uintptr_t tom;
@@ -60,7 +60,7 @@
return tom;
}
-u32 northbridge_get_tseg_size(void)
+static size_t northbridge_get_tseg_size(void)
{
const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC);
return decode_tseg_size(esmramc);
@@ -89,14 +89,10 @@
return ggc2uma[gms] << 10;
}
-void stage_cache_external_region(void **base, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
{
- /* The stage cache lives at the end of the TSEG region.
- * The top of RAM is defined to be the TSEG base address.
- */
- *size = CONFIG_SMM_RESERVED_SIZE;
- *base = (void *)((uintptr_t)northbridge_get_tseg_base()
- + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
+ *start = northbridge_get_tseg_base();
+ *size = northbridge_get_tseg_size();
}
void fill_postcar_frame(struct postcar_frame *pcf)
diff --git a/src/northbridge/intel/nehalem/memmap.c b/src/northbridge/intel/nehalem/memmap.c
index 1687ddf..fd10542 100644
--- a/src/northbridge/intel/nehalem/memmap.c
+++ b/src/northbridge/intel/nehalem/memmap.c
@@ -21,8 +21,8 @@
#include <cbmem.h>
#include <console/console.h>
#include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
#include <program_loading.h>
-#include <stage_cache.h>
#include <cpu/intel/smm_reloc.h>
#include "nehalem.h"
@@ -33,12 +33,12 @@
return tom;
}
-u32 northbridge_get_tseg_base(void)
+static uintptr_t northbridge_get_tseg_base(void)
{
- return (u32)smm_region_start();
+ return smm_region_start();
}
-u32 northbridge_get_tseg_size(void)
+static size_t northbridge_get_tseg_size(void)
{
return CONFIG_SMM_TSEG_SIZE;
}
@@ -48,13 +48,10 @@
return (void *) smm_region_start();
}
-void stage_cache_external_region(void **base, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
{
- /* The stage cache lives at the end of TSEG region.
- * The top of RAM is defined to be the TSEG base address. */
- *size = CONFIG_SMM_RESERVED_SIZE;
- *base = (void *)((uintptr_t)northbridge_get_tseg_base() +
- northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
+ *start = northbridge_get_tseg_base();
+ *size = northbridge_get_tseg_size();
}
void fill_postcar_frame(struct postcar_frame *pcf)
diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c
index 9908f11..b4fef6b 100644
--- a/src/northbridge/intel/pineview/memmap.c
+++ b/src/northbridge/intel/pineview/memmap.c
@@ -24,9 +24,9 @@
#include <cbmem.h>
#include <northbridge/intel/pineview/pineview.h>
#include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
#include <cpu/intel/smm_reloc.h>
#include <stdint.h>
-#include <stage_cache.h>
u8 decode_pciebar(u32 *const base, u32 *const len)
{
@@ -116,13 +116,13 @@
}
}
-u32 northbridge_get_tseg_size(void)
+static size_t northbridge_get_tseg_size(void)
{
const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC);
return decode_tseg_size(esmramc);
}
-u32 northbridge_get_tseg_base(void)
+static uintptr_t northbridge_get_tseg_base(void)
{
return pci_read_config32(PCI_DEV(0, 0, 0), TSEG);
}
@@ -139,14 +139,10 @@
}
-void stage_cache_external_region(void **base, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
{
- /* The stage cache lives at the end of the TSEG region.
- * The top of RAM is defined to be the TSEG base address.
- */
- *size = CONFIG_SMM_RESERVED_SIZE;
- *base = (void *)((uintptr_t)northbridge_get_tseg_base()
- + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
+ *start = northbridge_get_tseg_base();
+ *size = northbridge_get_tseg_size();
}
void fill_postcar_frame(struct postcar_frame *pcf)
diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c
index fa29b37..95bf458 100644
--- a/src/northbridge/intel/sandybridge/memmap.c
+++ b/src/northbridge/intel/sandybridge/memmap.c
@@ -21,8 +21,8 @@
#include <console/console.h>
#include <cpu/intel/smm_reloc.h>
#include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
#include <program_loading.h>
-#include <stage_cache.h>
#include "sandybridge.h"
static uintptr_t smm_region_start(void)
@@ -37,23 +37,20 @@
return (void *) smm_region_start();
}
-u32 northbridge_get_tseg_base(void)
+static uintptr_t northbridge_get_tseg_base(void)
{
return ALIGN_DOWN(smm_region_start(), 1*MiB);
}
-u32 northbridge_get_tseg_size(void)
+static size_t northbridge_get_tseg_size(void)
{
return CONFIG_SMM_TSEG_SIZE;
}
-void stage_cache_external_region(void **base, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
{
- /* The stage cache lives at the end of TSEG region.
- * The top of RAM is defined to be the TSEG base address. */
- *size = CONFIG_SMM_RESERVED_SIZE;
- *base = (void *)((uintptr_t)northbridge_get_tseg_base() + northbridge_get_tseg_size()
- - CONFIG_IED_REGION_SIZE - CONFIG_SMM_RESERVED_SIZE);
+ *start = northbridge_get_tseg_base();
+ *size = northbridge_get_tseg_size();
}
void fill_postcar_frame(struct postcar_frame *pcf)
diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c
index 2f50768..41e4912 100644
--- a/src/northbridge/intel/x4x/memmap.c
+++ b/src/northbridge/intel/x4x/memmap.c
@@ -25,10 +25,10 @@
#include <device/pci_def.h>
#include <console/console.h>
#include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
#include <northbridge/intel/x4x/x4x.h>
#include <program_loading.h>
#include <cpu/intel/smm_reloc.h>
-#include <stage_cache.h>
/** Decodes used Graphics Mode Select (GMS) to kilobytes. */
u32 decode_igd_memory_size(const u32 gms)
@@ -112,13 +112,13 @@
return 1;
}
-u32 northbridge_get_tseg_size(void)
+static size_t northbridge_get_tseg_size(void)
{
const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC);
return decode_tseg_size(esmramc);
}
-u32 northbridge_get_tseg_base(void)
+static uintptr_t northbridge_get_tseg_base(void)
{
return pci_read_config32(PCI_DEV(0, 0, 0), D0F0_TSEG);
}
@@ -134,14 +134,10 @@
return (void *) top_of_ram;
}
-void stage_cache_external_region(void **base, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
{
- /* The stage cache lives at the end of the TSEG region.
- * The top of RAM is defined to be the TSEG base address.
- */
- *size = CONFIG_SMM_RESERVED_SIZE;
- *base = (void *)((uintptr_t)northbridge_get_tseg_base()
- + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
+ *start = northbridge_get_tseg_base();
+ *size = northbridge_get_tseg_size();
}
void fill_postcar_frame(struct postcar_frame *pcf)