mb/clevo/n130wu: Use device alias names in devicetree
Switch to device alias names in devicetree. Remove unnecessary comments
since the names are self-explanatory.
Change-Id: Id486d9bd44bd7ba6a93a5f757af487b211e58efa
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
index 0a0cdf4..607e586 100644
--- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
+++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
@@ -44,10 +44,10 @@
end
device domain 0 on
subsystemid 0x1558 0x1313 inherit
- device pci 00.0 on end # Host Bridge
- device pci 02.0 on end # Integrated Graphics Device
- device pci 04.0 on end # SA thermal subsystem
- device pci 14.0 on # USB xHCI
+ device ref system_agent on end
+ device ref igpu on end
+ device ref sa_thermal on end
+ device ref south_xhci on
register "SsicPortEnable" = "0"
# USB2
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A, right
@@ -63,19 +63,19 @@
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type C, right
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, left
end
- device pci 14.2 on end # Thermal Subsystem
- device pci 16.0 on # Management Engine Interface 1
+ device ref thermal on end
+ device ref heci1 on
register "HeciEnabled" = "1"
end
- device pci 17.0 on # SATA
+ device ref sata on
register "SataSalpSupport" = "0"
# Ports
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[2]" = "1"
register "SataPortsDevSlp[2]" = "1"
end
- device pci 19.0 on end # UART 2
- device pci 1c.0 on # PCI Express Port 1
+ device ref uart2 on end
+ device ref pcie_rp1 on
device pci 00.0 on end # x4 TBT
register "PcieRpEnable[0]" = "1"
register "PcieRpClkReqSupport[0]" = "1"
@@ -85,7 +85,7 @@
register "PcieRpLtrEnable[0]" = "1"
smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthOther" "Thunderbolt/Type-C" "SlotDataBusWidth4X"
end
- device pci 1c.4 on # PCI Express Port 5
+ device ref pcie_rp5 on
device pci 00.0 on end # x1 LAN
register "PcieRpEnable[4]" = "1"
register "PcieRpClkReqSupport[4]" = "1"
@@ -93,7 +93,7 @@
register "PcieRpClkSrcNumber[4]" = "3"
register "PcieRpLtrEnable[4]" = "1"
end
- device pci 1c.5 on # PCI Express Port 6
+ device ref pcie_rp6 on
device pci 00.0 on end # x1 WLAN
register "PcieRpEnable[5]" = "1"
register "PcieRpClkReqSupport[5]" = "1"
@@ -102,7 +102,7 @@
register "PcieRpLtrEnable[5]" = "1"
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/A/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
end
- device pci 1d.0 on # PCI Express Port 9
+ device ref pcie_rp9 on
device pci 00.0 on end # x4 M.2/M (J_SSD1)
register "PcieRpEnable[8]" = "1"
register "PcieRpClkReqSupport[8]" = "1"
@@ -111,7 +111,7 @@
register "PcieRpLtrEnable[8]" = "1"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
end
- device pci 1f.0 on # LPC Interface
+ device ref lpc_espi on
register "gen1_dec" = "0x000c0681"
register "gen2_dec" = "0x000c1641"
register "gen3_dec" = "0x00040069"
@@ -120,14 +120,14 @@
device pnp 0c31.0 on end
end
end
- device pci 1f.1 hidden end # P2SB
- device pci 1f.2 on # Power Management Controller
+ device ref p2sb hidden end
+ device ref pmc on
register "gpe0_dw0" = "GPP_C"
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
end
- device pci 1f.3 on end # Intel HDA
- device pci 1f.4 on end # SMBus
- device pci 1f.5 on end # PCH SPI
+ device ref hda on end
+ device ref smbus on end
+ device ref fast_spi on end
end
end