soc/intel/meteorlake: Avoid redundant chipset programming in romstage
This patch refactors the mainboard_romstage_entry() function to avoid
redundant chipset programming caused by global reset due to CSE FW
sync operation. Hence, keeping only the minimal and mandatory
operations required to perform CSE FW sync successfully.
This would help to optimize the boot flow by removing redundant
programming like SA, SMBUS twice in every CSE FW update path.
TEST=Able to build and boot Google/Rex successfully.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1a13fac1e99341991d8dd818d4ab8a20d209a94c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71933
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/meteorlake/romstage/romstage.c b/src/soc/intel/meteorlake/romstage/romstage.c
index 35f9368..340716f 100644
--- a/src/soc/intel/meteorlake/romstage/romstage.c
+++ b/src/soc/intel/meteorlake/romstage/romstage.c
@@ -119,23 +119,23 @@
void mainboard_romstage_entry(void)
{
- bool s3wake;
struct chipset_power_state *ps = pmc_get_power_state();
+ bool s3wake = pmc_fill_power_state(ps) == ACPI_S3;
- /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
- systemagent_early_init();
- /* Program SMBus base address and enable it */
- smbus_common_init();
/* Initialize HECI interface */
cse_init(HECI1_BASE_ADDRESS);
- s3wake = pmc_fill_power_state(ps) == ACPI_S3;
if (!s3wake && CONFIG(SOC_INTEL_CSE_LITE_SKU)) {
timestamp_add_now(TS_CSE_FW_SYNC_START);
cse_fw_sync();
timestamp_add_now(TS_CSE_FW_SYNC_END);
}
+ /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
+ systemagent_early_init();
+ /* Program SMBus base address and enable it */
+ smbus_common_init();
+
/*
* Set low maximum temp threshold value used for dynamic thermal sensor
* shutdown consideration.