commit d450609145a78c2d93707664073466bf29c83426
author Elyes HAOUAS <ehaouas@noos.fr> Thu May 26 19:53:29 2016 +0200
committer Stefan Reinauer <stefan.reinauer@coreboot.org> Tue Jun 14 23:54:51 2016 +0200
tree 61ec843b9fc69b43f28bec215d53ebc0fcfb77f0
parent 579fdb4910aaac3e29f55b44f5333b4a9416d3be

Added CL7 support

according to "JEDEC_DDR2_SPD_Specification_Rev1.3.pdf"
Annex J: Serial Presence Detects for DDR2 SDRAM (Revision 1.3)
page 16 and page 60, CL7 support added

Change-Id: I22aaf064ab8767755f74dfdb44e32d13fc61b2c4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/14976
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/include/spd.h

diff --git a/src/include/spd.h b/src/include/spd.h
index ea1b355..7aaf4dd 100644
--- a/src/include/spd.h
+++ b/src/include/spd.h
@@ -145,6 +145,7 @@
 #define SPD_CAS_LATENCY_DDR2_4		(1 << 4)
 #define SPD_CAS_LATENCY_DDR2_5		(1 << 5)
 #define SPD_CAS_LATENCY_DDR2_6		(1 << 6)
+#define SPD_CAS_LATENCY_DDR2_7		(1 << 7)
 
 /* SPD_SUPPORTED_BURST_LENGTHS values. */
 #define SPD_BURST_LENGTH_1               1