mb/google/rex/var/ovis: Enable LAN0
This patch performs below operations to enable LAN0.
- Complete the LAN PEREST power sequencing
- Program the SRC_CLKREQ (GPP_D20) with correctly.
- Add overridetree.cb entry to configure the LAN0 device.
BUG=b:289395519
TEST=Able to boot google/ovis with LAN0 being enabled.
Change-Id: I91b0a76395ade4459cf8705c333728a71f95df14
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76213
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/google/rex/variants/ovis/gpio.c b/src/mainboard/google/rex/variants/ovis/gpio.c
index 6c1794d..b86307f 100644
--- a/src/mainboard/google/rex/variants/ovis/gpio.c
+++ b/src/mainboard/google/rex/variants/ovis/gpio.c
@@ -188,8 +188,8 @@
PAD_CFG_GPI_APIC_LOCK(GPP_D18, NONE, LEVEL, INVERT, LOCK_CONFIG),
/* GPP_D19 : [] ==> SSD_CLKREQ_ODL */
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
- /* GPP_D20 : [] ==> EN_LAN_RAILS */
- PAD_NC(GPP_D20, NONE),
+ /* GPP_D20 : [] ==> LAN_CLKREQ_ODL */
+ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
/* GPP_D21 : [] ==> WLAN_CLKREQ_ODL */
PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2),
/* GPP_D22 : [] ==> NC */
@@ -398,6 +398,9 @@
/* GPP_A20 : [] ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_A20, 0, DEEP),
+ /* GPP_C13 : [] ==> LAN_PERST_L */
+ PAD_CFG_GPO(GPP_C13, 0, DEEP),
+
/* GPP_H10 : [] ==> SOC_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG),
@@ -406,6 +409,8 @@
};
static const struct pad_config romstage_gpio_table[] = {
+ /* GPP_C13 : [] ==> LAN_PERST_L */
+ PAD_CFG_GPO(GPP_C13, 0, DEEP),
/* A20 : [] ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_A20, 0, DEEP),
/* GPP_D02 : [] ==> SD_PERST_L */
diff --git a/src/mainboard/google/rex/variants/ovis/overridetree.cb b/src/mainboard/google/rex/variants/ovis/overridetree.cb
index 259aaf5..112072c 100644
--- a/src/mainboard/google/rex/variants/ovis/overridetree.cb
+++ b/src/mainboard/google/rex/variants/ovis/overridetree.cb
@@ -63,7 +63,14 @@
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end #PCIE7 LAN1 card
-
+ device ref pcie_rp10 on
+ # Enable LAN0 Card PCIE 10 using clk 8
+ register "pcie_rp[PCH_RP(10)]" = "{
+ .clk_src = 8,
+ .clk_req = 8,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ end #PCIE10 LAN0 card
device ref pcie_rp11 on
# Enable SSD Card PCIE 11 using clk 7
register "pcie_rp[PCH_RP(11)]" = "{