AGESA: Avoid cpuRegisters.h include
Change-Id: I077677c10508a89a79bcb580249c1310e319aaf1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c
index 4dbe86d..735e126 100644
--- a/src/northbridge/amd/agesa/family15/northbridge.c
+++ b/src/northbridge/amd/agesa/family15/northbridge.c
@@ -35,7 +35,6 @@
#include <AGESA.h>
#include <Options.h>
#include <Topology.h>
-#include <cpuRegisters.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/state_machine.h>
@@ -931,7 +930,7 @@
#endif
/* Get Max Number of cores(MNC) */
- coreid_bits = (cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT) & 0x0000F000) >> 12;
+ coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12;
core_max = 1 << (coreid_bits & 0x000F); //mnc
ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF);
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c
index e82dae1..675be14 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -36,7 +36,6 @@
#include <Porting.h>
#include <Options.h>
#include <Topology.h>
-#include <cpuRegisters.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/state_machine.h>
@@ -921,7 +920,7 @@
#endif
/* Get Max Number of cores(MNC) */
- coreid_bits = (cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT) & 0x0000F000) >> 12;
+ coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12;
core_max = 1 << (coreid_bits & 0x000F); //mnc
ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF);
diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c
index 77215b4..557c9c4 100644
--- a/src/northbridge/amd/agesa/family16kb/northbridge.c
+++ b/src/northbridge/amd/agesa/family16kb/northbridge.c
@@ -35,7 +35,6 @@
#include <AGESA.h>
#include <Options.h>
#include <Topology.h>
-#include <cpuRegisters.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/state_machine.h>
@@ -937,7 +936,7 @@
#endif
/* Get Max Number of cores(MNC) */
- coreid_bits = (cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT) & 0x0000F000) >> 12;
+ coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12;
core_max = 1 << (coreid_bits & 0x000F); //mnc
ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF);
diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c
index cb90cb6..f24a481 100644
--- a/src/northbridge/amd/pi/00630F01/northbridge.c
+++ b/src/northbridge/amd/pi/00630F01/northbridge.c
@@ -32,7 +32,6 @@
#include <FieldAccessors.h>
#include <Options.h>
#include <Topology.h>
-#include <cpuRegisters.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
#include <northbridge/amd/pi/agesawrapper.h>
@@ -935,7 +934,7 @@
#endif
/* Get Max Number of cores(MNC) */
- coreid_bits = (cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT) & 0x0000F000) >> 12;
+ coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12;
core_max = 1 << (coreid_bits & 0x000F); //mnc
ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF);
diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c
index 1f2c28e..6a2cb8f 100644
--- a/src/northbridge/amd/pi/00660F01/northbridge.c
+++ b/src/northbridge/amd/pi/00660F01/northbridge.c
@@ -32,7 +32,6 @@
#include <FieldAccessors.h>
#include <Options.h>
#include <Topology.h>
-#include <cpuRegisters.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
#include <northbridge/amd/pi/agesawrapper.h>
@@ -934,7 +933,7 @@
#endif
/* Get Max Number of cores(MNC) */
- coreid_bits = (cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT) & 0x0000F000) >> 12;
+ coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12;
core_max = 1 << (coreid_bits & 0x000F); //mnc
ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF);
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index 9014f29..a762e2c 100644
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -32,7 +32,6 @@
#include <FieldAccessors.h>
#include <Options.h>
#include <Topology.h>
-#include <cpuRegisters.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
#include <northbridge/amd/pi/agesawrapper.h>
@@ -960,7 +959,7 @@
#endif
/* Get Max Number of cores(MNC) */
- coreid_bits = (cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT) & 0x0000F000) >> 12;
+ coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12;
core_max = 1 << (coreid_bits & 0x000F); //mnc
ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF);
diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c
index 2fb708b..d912317 100644
--- a/src/northbridge/amd/pi/agesawrapper.c
+++ b/src/northbridge/amd/pi/agesawrapper.c
@@ -18,7 +18,6 @@
#include <cbmem.h>
#include <delay.h>
#include <cpu/x86/mtrr.h>
-#include <cpuRegisters.h>
#include <FchPlatform.h>
#include <heapManager.h>
#include <northbridge/amd/agesa/agesa_helper.h>
diff --git a/src/soc/amd/common/agesawrapper.c b/src/soc/amd/common/agesawrapper.c
index 3ad4871..b95d61a 100644
--- a/src/soc/amd/common/agesawrapper.c
+++ b/src/soc/amd/common/agesawrapper.c
@@ -18,7 +18,6 @@
#include <cbmem.h>
#include <delay.h>
#include <cpu/x86/mtrr.h>
-#include <cpuRegisters.h>
#include <FchPlatform.h>
#include <heapManager.h>
#include <agesawrapper.h>
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index c0f5850..d9cc281 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -40,7 +40,6 @@
* and not set by vendorcode
*/
#include <AGESA.h>
-#include <cpuRegisters.h>
#include <FieldAccessors.h>
#include <Options.h>
#include <Porting.h>
@@ -573,7 +572,7 @@
}
/* Get max and actual number of cores */
- pccount = cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT);
+ pccount = cpuid_ecx(0x80000008);
core_max = 1 << ((pccount >> 12) & 0xf);
core_nums = (pccount & 0xF);