Drop the need for cpu_reset, it's really just a short cut to stage2.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5393 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c
index ed8e647..d5d00a9 100644
--- a/src/mainboard/intel/mtarvon/romstage.c
+++ b/src/mainboard/intel/mtarvon/romstage.c
@@ -58,6 +58,7 @@
#include "northbridge/intel/i3100/raminit.c"
#include "lib/generic_sdram.c"
#include "../jarrell/debug.c"
+#include "arch/i386/lib/stages.c"
static void main(unsigned long bist)
{
@@ -79,7 +80,7 @@
/* Skip this if there was a built in self test failure */
early_mtrr_init();
if (memory_initialized()) {
- asm volatile ("jmp __cpu_reset");
+ skip_romstage();
}
}
/* Set up the console */