diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h
index 140ea20..adf53ea 100644
--- a/src/northbridge/intel/haswell/raminit.h
+++ b/src/northbridge/intel/haswell/raminit.h
@@ -3,11 +3,15 @@
 #ifndef RAMINIT_H
 #define RAMINIT_H
 
+#include <stdint.h>
 #include "pei_data.h"
 
 /* Optional function to copy SPD data for on-board memory */
 void copy_spd(struct pei_data *peid);
 
+/* Mainboard callback to fill in the SPD addresses in MRC format */
+void mb_get_spd_map(uint8_t spd_map[4]);
+
 /* Necessary function to initialize pei_data with mainboard-specific settings */
 void mainboard_fill_pei_data(struct pei_data *pei_data);
 
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c
index 40b7b87..2961299 100644
--- a/src/northbridge/intel/haswell/romstage.c
+++ b/src/northbridge/intel/haswell/romstage.c
@@ -87,6 +87,9 @@
 	/* MRC has hardcoded assumptions of 2 meaning S3 wake. Normalize it here. */
 	pei_data.boot_mode = wake_from_s3 ? 2 : 0;
 
+	/* Obtain the SPD addresses from mainboard code */
+	mb_get_spd_map(pei_data.spd_addresses);
+
 	/* Calculate unimplemented DIMM slots for each channel */
 	pei_data.dimm_channel0_disabled = make_channel_disabled_mask(&pei_data, 0);
 	pei_data.dimm_channel1_disabled = make_channel_disabled_mask(&pei_data, 1);