soc/soc/intel: Add UFS device with ref-clk-freq property
UFS storage devices require the bRefClkFreq attribute to be set to
operate correctly in high speed mode. The correct value is determined by
what the SoC / board supports. For the ADL UFS controller, it is
19.2 MHz.
a) Introduce a new ACPI property "ref-clk-freq".
b) Add support to configure this property using an SoC Kconfig.
Kernel patch:
https://web.archive.org/web/20220801060732/https://lore.kernel.org/all/
20220715210230.1.I365d113d275117dee8fd055ce4fc7e6aebd0bce9@changeid/
BUG=b:238262674
TEST=Build,boot Nirwen and dump SSDT entries and check that the kernel
correctly parses ref-clk-freq as 19.2 MHz.
Scope (\_SB.PCI0)
{
Device (UFS)
{
Name (_ADR, 0x0000000000120007) // _ADR: Address
Name (_DDN, "UFS Controller") // _DDN: DOS Device Name
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301")
/* Device Properties for _DSD */,
Package (0x01)
{
Package (0x02)
{
"ref-clk-freq",
0x0124F800
}
}
})
}
}
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Change-Id: I80c338a8a61f161b0feb6c5a3ca00cf5e0cfb36c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index af1a049..5a6df8d 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -295,6 +295,10 @@
config CPU_XTAL_HZ
default 38400000
+config SOC_INTEL_UFS_CLK_FREQ_HZ
+ int
+ default 19200000
+
config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
int
default 133
diff --git a/src/soc/intel/common/block/scs/Kconfig b/src/soc/intel/common/block/scs/Kconfig
index 192425c..6b5f49e 100644
--- a/src/soc/intel/common/block/scs/Kconfig
+++ b/src/soc/intel/common/block/scs/Kconfig
@@ -19,3 +19,10 @@
help
Override the MMC settings after FSP-S.
It should be used only when there is no FSP UPDs for certain setting.
+
+config SOC_INTEL_COMMON_UFS_SUPPORT
+ bool
+ default n
+ help
+ Enable UFS support. Should be enabled when a particular SoC supports
+ boot from UFS.
diff --git a/src/soc/intel/common/block/scs/Makefile.inc b/src/soc/intel/common/block/scs/Makefile.inc
index 0b77f5f..aa5f2b5 100644
--- a/src/soc/intel/common/block/scs/Makefile.inc
+++ b/src/soc/intel/common/block/scs/Makefile.inc
@@ -2,4 +2,5 @@
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SCS) += sd.c
endif
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SCS) += mmc.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_UFS_SUPPORT) += ufs.c
romstage-$(CONFIG_SOC_INTEL_COMMON_EARLY_MMC_WAKE) += early_mmc.c
diff --git a/src/soc/intel/common/block/scs/ufs.c b/src/soc/intel/common/block/scs/ufs.c
new file mode 100644
index 0000000..e70c87b
--- /dev/null
+++ b/src/soc/intel/common/block/scs/ufs.c
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_device.h>
+#include <acpi/acpigen.h>
+#include <acpi/acpigen_pci.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+#if CONFIG(HAVE_ACPI_TABLES)
+static void ufs_fill_ssdt(const struct device *dev)
+{
+ struct acpi_dp *dsd;
+
+ const char *scope = acpi_device_scope(dev);
+
+ acpigen_write_scope(scope);
+ acpigen_write_device("UFS");
+ acpigen_write_ADR_pci_device(dev);
+ acpigen_write_name_string("_DDN", "UFS Controller");
+
+ dsd = acpi_dp_new_table("_DSD");
+ acpi_dp_add_integer(dsd, "ref-clk-freq", CONFIG_SOC_INTEL_UFS_CLK_FREQ_HZ);
+ acpi_dp_write(dsd);
+ acpigen_write_device_end();
+ acpigen_pop_len();
+}
+#endif
+
+static struct device_operations dev_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+#if CONFIG(HAVE_ACPI_TABLES)
+ .acpi_fill_ssdt = ufs_fill_ssdt,
+#endif
+ .ops_pci = &pci_dev_ops_pci,
+};
+
+static const unsigned short pci_device_ids[] = {
+ PCI_DID_INTEL_ADP_UFS,
+ 0
+};
+
+static const struct pci_driver pch_ufs __pci_driver = {
+ .ops = &dev_ops,
+ .vendor = PCI_VID_INTEL,
+ .devices = pci_device_ids
+};