soc/intel/jasperlake: Enable wake from USB
Use the common UWES ACPI method to enable wake from USB. The only
difference to other SoCs is that JSL only has 8 USB2 ports, so the USB3
PORTSC register offset is different.
BUG=b:300844110
TEST=When enabled on taranza, all USB2 and USB3 ports can wake from
suspend
Change-Id: Ibc90246965d5d809123e954847543d28d78498a5
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78086
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
diff --git a/src/soc/intel/jasperlake/acpi/xhci.asl b/src/soc/intel/jasperlake/acpi/xhci.asl
index 8ecbe47..acaf450 100644
--- a/src/soc/intel/jasperlake/acpi/xhci.asl
+++ b/src/soc/intel/jasperlake/acpi/xhci.asl
@@ -2,6 +2,15 @@
#include <soc/gpe.h>
+/*
+ * JSL has 8 USB2 ports, so the USB3 PORTSC registers start at
+ * 0x480 + 8 * 0x10 = 0x500
+ */
+#define JSL_PORTSCXUSB3_OFFSET 0x500
+
+/* Include UWES method for enabling USB wake */
+#include <soc/intel/common/acpi/xhci_wake.asl>
+
/* XHCI Controller 0:14.0 */
Device (XHCI)
@@ -10,6 +19,20 @@
Name (_PRW, Package () { GPE0_PME_B0, 3 })
+ OperationRegion (XPRT, PCI_Config, 0x00, 0x100)
+ Field (XPRT, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x10),
+ , 16,
+ XMEM, 16, /* MEM_BASE */
+ }
+
+ Method (_DSW, 3)
+ {
+ UWES ((\U2WE & 0xFF), PORTSCN_OFFSET, XMEM)
+ UWES ((\U3WE & 0x3F ), JSL_PORTSCXUSB3_OFFSET, XMEM)
+ }
+
Name (_S3D, 3) /* D3 supported in S3 */
Name (_S0W, 3) /* D3 can wake device in S0 */
Name (_S3W, 3) /* D3 can wake system from S3 */
diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
index 2af85e3..66ad223 100644
--- a/src/soc/intel/jasperlake/chip.h
+++ b/src/soc/intel/jasperlake/chip.h
@@ -11,6 +11,7 @@
#include <intelblocks/gspi.h>
#include <intelblocks/pcie_rp.h>
#include <intelblocks/power_limit.h>
+#include <intelblocks/xhci.h>
#include <soc/gpe.h>
#include <soc/pch.h>
#include <soc/pci_devs.h>