soc/intel/cse: Select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE when PSR enabled
PSR data is created and stored in CSE data partition. In platforms that
employ CSE Lite SKU firmware, a firmware downgrade involves clearing of
CSE data partition which results in PSR data being lost. The PSR data
needs to be preserved across the firmware downgrade flow. CSE Lite SKU
firmware supports command to backup PSR data, and this command can be
sent only in post-RAM stages. So the cse_fw_sync actions needs to be
moved to ramstage.
This patch ensures SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE is selected when
PSR is enabled.
BUG=b:273207144
Change-Id: I7c9bf8b8606cf68ec798ff35129e92cd60bbb137
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78055
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig
index e46becc..581cecd 100644
--- a/src/soc/intel/common/block/cse/Kconfig
+++ b/src/soc/intel/common/block/cse/Kconfig
@@ -144,10 +144,14 @@
bool
default n
depends on SOC_INTEL_CSE_LITE_SKU
+ select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE
help
Select this config if Platform Service Record(PSR) is supported by the platform. This
config is applicable only for Lite SKU, where PSR data backup is required prior to a
- CSE firmware downgrade during which CSE data is cleared.
+ CSE firmware downgrade during which CSE data is cleared. PSR services in CSE FW is
+ enabled only post DRAM init and the command to backup PSR data is also supported only
+ post DRAM init. Hence platform that selects PSR would need to perform CSE firmware sync
+ in ramstage.
config SOC_INTEL_CSE_SERVER_SKU
bool