tree 382a06863e41a9b1d29980eb7ff51fb64a2aa40a
parent 815d96a975d67db73b8299b3c521b74cf9725b99
author Wonkyu Kim <wonkyu.kim@intel.com> 1579672454 -0800
committer Subrata Banik <subrata.banik@intel.com> 1579859594 +0000

mb/intel/tglrvp: Enable SATA

Enable both SATA ports for TGLRVP.

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board with SATA memory

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I9f35682982a6c06522e58b0bbd7162ff02c37f32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38505
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>