northbridge/intel/i945/gma.c: Add and use defines for `GMADR` and `GTTADR`
Change-Id: I0f39b35fbf8e053ba21454a2847d6bb3ac5d2e1c
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5923
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index 453e9c8..1cf80a9 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -59,8 +59,8 @@
graphics_base = dev->resource_list[2].base + 0x20000;
printk(BIOS_SPEW, "GMADR=0x%08x GTTADR=0x%08x\n",
- pci_read_config32(dev, 0x18),
- pci_read_config32(dev, 0x1c)
+ pci_read_config32(dev, GMADR),
+ pci_read_config32(dev, GTTADR)
);
int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx);
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index 8212386..9be9379 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -87,6 +87,8 @@
/* Device 0:2.0 PCI configuration space (Graphics Device) */
+#define GMADR 0x18
+#define GTTADR 0x1c
#define BSM 0x5c
#define GCFC 0xf0 /* Graphics Clock Frequency & Gating Control */