tree 2f9ccb52774aba1a0e0f9a2d85b59d52a5d1d9c0
parent 425d8640fa3d8e4a43bd9f2cc8f8fd7fedf675c3
author Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> 1589538337 +0530
committer Patrick Georgi <pgeorgi@google.com> 1589966051 +0000

tigerlake: update processor power limits configuration

Update processor power limit configuration parameters based on
common code base support for Intel Tigerlake SoC based platforms.

BRANCH=None
BUG=None
TEST=Built and tested on volteer system

Change-Id: Iccd387d78bb45ca3de73f531a901d1d3f793d7bd
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39345
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>