nb/intel/x4x: Define and use `HOST_BRIDGE` macro
Other Intel northbridges do this.
Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change
Change-Id: I50785b7bf3e3cc0eade7fda4b4b2e2bb71a54c31
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c
index 5db9382..328464a 100644
--- a/src/northbridge/intel/x4x/bootblock.c
+++ b/src/northbridge/intel/x4x/bootblock.c
@@ -13,5 +13,5 @@
reg32 = TPM32(0);
reg32 = CONFIG_MMCONF_BASE_ADDRESS | 16 | 1;
- pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO, reg32);
+ pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, reg32);
}
diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c
index 87c684c..d3c3308 100644
--- a/src/northbridge/intel/x4x/early_init.c
+++ b/src/northbridge/intel/x4x/early_init.c
@@ -15,32 +15,30 @@
void x4x_early_init(void)
{
- const pci_devfn_t d0f0 = PCI_DEV(0, 0, 0);
-
/* Setup MCHBAR. */
- pci_write_config32(d0f0, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1);
+ pci_write_config32(HOST_BRIDGE, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1);
/* Setup DMIBAR. */
- pci_write_config32(d0f0, D0F0_DMIBAR_LO, (uintptr_t)DEFAULT_DMIBAR | 1);
+ pci_write_config32(HOST_BRIDGE, D0F0_DMIBAR_LO, (uintptr_t)DEFAULT_DMIBAR | 1);
/* Setup EPBAR. */
- pci_write_config32(d0f0, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1);
+ pci_write_config32(HOST_BRIDGE, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1);
/* Setup HECIBAR */
pci_write_config32(PCI_DEV(0, 3, 0), 0x10, DEFAULT_HECIBAR);
/* Set C0000-FFFFF to access RAM on both reads and writes */
- pci_write_config8(d0f0, D0F0_PAM(0), 0x30);
- pci_write_config8(d0f0, D0F0_PAM(1), 0x33);
- pci_write_config8(d0f0, D0F0_PAM(2), 0x33);
- pci_write_config8(d0f0, D0F0_PAM(3), 0x33);
- pci_write_config8(d0f0, D0F0_PAM(4), 0x33);
- pci_write_config8(d0f0, D0F0_PAM(5), 0x33);
- pci_write_config8(d0f0, D0F0_PAM(6), 0x33);
+ pci_write_config8(HOST_BRIDGE, D0F0_PAM(0), 0x30);
+ pci_write_config8(HOST_BRIDGE, D0F0_PAM(1), 0x33);
+ pci_write_config8(HOST_BRIDGE, D0F0_PAM(2), 0x33);
+ pci_write_config8(HOST_BRIDGE, D0F0_PAM(3), 0x33);
+ pci_write_config8(HOST_BRIDGE, D0F0_PAM(4), 0x33);
+ pci_write_config8(HOST_BRIDGE, D0F0_PAM(5), 0x33);
+ pci_write_config8(HOST_BRIDGE, D0F0_PAM(6), 0x33);
- if (!(pci_read_config32(d0f0, D0F0_CAPID0 + 4) & (1 << (46 - 32)))) {
+ if (!(pci_read_config32(HOST_BRIDGE, D0F0_CAPID0 + 4) & (1 << (46 - 32)))) {
/* Enable internal GFX */
- pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN);
+ pci_write_config32(HOST_BRIDGE, D0F0_DEVEN, BOARD_DEVEN);
/* Set preallocated IGD size from CMOS */
u8 gfxsize = 6; /* 6 for 64MiB, default if not set in CMOS */
@@ -51,10 +49,10 @@
else if (gfxsize < 1)
gfxsize = 1;
/* Set GTT size to 2+2M */
- pci_write_config16(d0f0, D0F0_GGC, 0x0b00 | (gfxsize + 1) << 4);
+ pci_write_config16(HOST_BRIDGE, D0F0_GGC, 0x0b00 | (gfxsize + 1) << 4);
} else { /* Does not feature internal graphics */
- pci_write_config32(d0f0, D0F0_DEVEN, D0EN | D1EN | PEG1EN);
- pci_write_config16(d0f0, D0F0_GGC, (1 << 1));
+ pci_write_config32(HOST_BRIDGE, D0F0_DEVEN, D0EN | D1EN | PEG1EN);
+ pci_write_config16(HOST_BRIDGE, D0F0_GGC, (1 << 1));
}
}
diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c
index 8a69ba8..db0ab9c 100644
--- a/src/northbridge/intel/x4x/memmap.c
+++ b/src/northbridge/intel/x4x/memmap.c
@@ -72,7 +72,7 @@
{0, 0},
};
- const u32 pciexbar_reg = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO);
+ const u32 pciexbar_reg = pci_read_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO);
if (!(pciexbar_reg & 1)) {
printk(BIOS_WARNING, "WARNING: MMCONF not set\n");
@@ -95,13 +95,13 @@
static size_t northbridge_get_tseg_size(void)
{
- const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC);
+ const u8 esmramc = pci_read_config8(HOST_BRIDGE, D0F0_ESMRAMC);
return decode_tseg_size(esmramc);
}
static uintptr_t northbridge_get_tseg_base(void)
{
- return pci_read_config32(PCI_DEV(0, 0, 0), D0F0_TSEG);
+ return pci_read_config32(HOST_BRIDGE, D0F0_TSEG);
}
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index 174e8b5..9f361b6 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -122,11 +122,11 @@
const u32 eax = cpuid_ext(0x04, 0).eax;
printk(BIOS_WARNING, "%d CPU cores\n", ((eax >> 26) & 0x3f) + 1);
- u32 capid = pci_read_config16(PCI_DEV(0, 0, 0), 0xe8);
+ u32 capid = pci_read_config16(HOST_BRIDGE, 0xe8);
if (!(capid & (1<<(79-64))))
printk(BIOS_WARNING, "iTPM enabled\n");
- capid = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4);
+ capid = pci_read_config32(HOST_BRIDGE, 0xe4);
if (!(capid & (1<<(57-32))))
printk(BIOS_WARNING, "ME enabled\n");
@@ -246,7 +246,7 @@
u32 min_tCLK;
u8 try_CAS;
- u16 capid = (pci_read_config16(PCI_DEV(0, 0, 0), 0xea) >> 4) & 0x3f;
+ u16 capid = (pci_read_config16(HOST_BRIDGE, 0xea) >> 4) & 0x3f;
switch (s->max_fsb) {
default:
@@ -344,7 +344,7 @@
if (s->selected_timings.mem_clk != MEM_CLOCK_1066MHz)
return;
/* IGD0EN gets disabled if not present before this code runs */
- deven = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN);
+ deven = pci_read_config32(HOST_BRIDGE, D0F0_DEVEN);
if (deven & IGD0EN)
s->stacked_mode = 1;
}
@@ -593,9 +593,9 @@
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2);
/* do magic 0xf0 thing. */
- pci_and_config8(PCI_DEV(0, 0, 0), 0xf0, ~(1 << 2));
+ pci_and_config8(HOST_BRIDGE, 0xf0, ~(1 << 2));
- pci_or_config8(PCI_DEV(0, 0, 0), 0xf0, (1 << 2));
+ pci_or_config8(HOST_BRIDGE, 0xf0, (1 << 2));
full_reset();
}
@@ -616,7 +616,7 @@
timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "Setting up RAM controller.\n");
- pci_write_config8(PCI_DEV(0, 0, 0), 0xdf, 0xff);
+ pci_write_config8(HOST_BRIDGE, 0xdf, 0xff);
memset(&s, 0, sizeof(struct sysinfo));
@@ -671,7 +671,7 @@
checkreset_ddr2(s.boot_path);
/* Detect dimms per channel */
- reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xe9);
+ reg8 = pci_read_config8(HOST_BRIDGE, 0xe9);
printk(BIOS_DEBUG, "Dimms per channel: %d\n",
(reg8 & 0x10) ? 1 : 2);
@@ -687,7 +687,7 @@
pci_and_config8(PCI_DEV(0, 0x1f, 0), 0xa2, (u8)~0x80);
- pci_or_config8(PCI_DEV(0, 0, 0), 0xf4, 1);
+ pci_or_config8(HOST_BRIDGE, 0xf4, 1);
printk(BIOS_DEBUG, "RAM initialization finished.\n");
diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c
index 332af32..1aa7e39 100644
--- a/src/northbridge/intel/x4x/raminit_ddr23.c
+++ b/src/northbridge/intel/x4x/raminit_ddr23.c
@@ -1270,14 +1270,14 @@
MCHBAR8(0x110) = (2 << 5) | (3 << 3);
MCHBAR16(0x10e) = 0;
MCHBAR32(0x108) = 0;
- pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOLUD, 0x4000);
+ pci_write_config16(HOST_BRIDGE, D0F0_TOLUD, 0x4000);
/* TOM(64M unit) = 1G = TOTAL_CHANNELS * RANKS_PER_CHANNEL * 128M */
- pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOM, 0x10);
+ pci_write_config16(HOST_BRIDGE, D0F0_TOM, 0x10);
/* TOUUD(1M unit) = 1G = TOTAL_CHANNELS * RANKS_PER_CHANNEL * 128M */
- pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOUUD, 0x0400);
- pci_write_config32(PCI_DEV(0, 0, 0), D0F0_GBSM, 0x40000000);
- pci_write_config32(PCI_DEV(0, 0, 0), D0F0_BGSM, 0x40000000);
- pci_write_config32(PCI_DEV(0, 0, 0), D0F0_TSEG, 0x40000000);
+ pci_write_config16(HOST_BRIDGE, D0F0_TOUUD, 0x0400);
+ pci_write_config32(HOST_BRIDGE, D0F0_GBSM, 0x40000000);
+ pci_write_config32(HOST_BRIDGE, D0F0_BGSM, 0x40000000);
+ pci_write_config32(HOST_BRIDGE, D0F0_TSEG, 0x40000000);
}
u32 test_address(int channel, int rank)
@@ -1702,7 +1702,7 @@
160, 224, 352 };
u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4};
- ggc = pci_read_config16(PCI_DEV(0, 0, 0), 0x52);
+ ggc = pci_read_config16(HOST_BRIDGE, 0x52);
gfxsize = ggc2uma[(ggc & 0xf0) >> 4];
gttsize = ggc2gtt[(ggc & 0xf00) >> 8];
/* TSEG 2M, This amount can easily be covered by SMRR MTRR's,
@@ -1733,20 +1733,20 @@
gttbase = gfxbase - gttsize;
tsegbase = gttbase - tsegsize;
- pci_write_config16(PCI_DEV(0, 0, 0), 0xb0, tolud << 4);
- pci_write_config16(PCI_DEV(0, 0, 0), 0xa0, tom >> 6);
+ pci_write_config16(HOST_BRIDGE, 0xb0, tolud << 4);
+ pci_write_config16(HOST_BRIDGE, 0xa0, tom >> 6);
if (reclaim) {
- pci_write_config16(PCI_DEV(0, 0, 0), 0x98,
+ pci_write_config16(HOST_BRIDGE, 0x98,
(u16)(reclaimbase >> 6));
- pci_write_config16(PCI_DEV(0, 0, 0), 0x9a,
+ pci_write_config16(HOST_BRIDGE, 0x9a,
(u16)(reclaimlimit >> 6));
}
- pci_write_config16(PCI_DEV(0, 0, 0), 0xa2, touud);
- pci_write_config32(PCI_DEV(0, 0, 0), 0xa4, gfxbase << 20);
- pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, gttbase << 20);
+ pci_write_config16(HOST_BRIDGE, 0xa2, touud);
+ pci_write_config32(HOST_BRIDGE, 0xa4, gfxbase << 20);
+ pci_write_config32(HOST_BRIDGE, 0xa8, gttbase << 20);
/* Enable and set TSEG size to 2M */
- pci_update_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, ~0x07, (1 << 1) | (1 << 0));
- pci_write_config32(PCI_DEV(0, 0, 0), 0xac, tsegbase << 20);
+ pci_update_config8(HOST_BRIDGE, D0F0_ESMRAMC, ~0x07, (1 << 1) | (1 << 0));
+ pci_write_config32(HOST_BRIDGE, 0xac, tsegbase << 20);
}
static void set_enhanced_mode(struct sysinfo *s)
@@ -1779,8 +1779,8 @@
MCHBAR32(0x400*ch + 0x290) = 0x4f2091c;
}
- reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0);
- pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | 1);
+ reg8 = pci_read_config8(HOST_BRIDGE, 0xf0);
+ pci_write_config8(HOST_BRIDGE, 0xf0, reg8 | 1);
MCHBAR32_AND_OR(0xfa0, ~0x20002, 0x2 | (s->selected_timings.fsb_clk ==
FSB_CLOCK_1333MHz ? 0x20000 : 0));
reg32 = 0x219100c2;
@@ -1822,7 +1822,7 @@
if (s->selected_timings.fsb_clk < FSB_CLOCK_1333MHz)
reg32 |= 0x20000;
MCHBAR32(0x20) = reg32;
- pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~1);
+ pci_write_config8(HOST_BRIDGE, 0xf0, reg8 & ~1);
}
static void power_settings(struct sysinfo *s)
@@ -1943,7 +1943,7 @@
MCHBAR32(0x1110) = 0x10810350 & ~0x78;
MCHBAR32(0x1114) = 0;
x592 = 0xff;
- if (pci_read_config8(PCI_DEV(0, 0, 0), 0x8) < 3)
+ if (pci_read_config8(HOST_BRIDGE, 0x8) < 3)
x592 = ~0x4;
FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {
@@ -2056,7 +2056,7 @@
MCHBAR8_OR(0x5d8, 0x7);
}
if (CHANNEL_IS_POPULATED(s->dimms, 1)) {
- if (pci_read_config8(PCI_DEV(0, 0, 0), 0x8) < 2) {
+ if (pci_read_config8(HOST_BRIDGE, 0x8) < 2) {
MCHBAR8_AND_OR(0x5dd, ~0x3f, 0x3f);
MCHBAR8_OR(0x5d8, 1);
}
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h
index bb51c60..45785a0 100644
--- a/src/northbridge/intel/x4x/x4x.h
+++ b/src/northbridge/intel/x4x/x4x.h
@@ -9,6 +9,8 @@
/*
* D0:F0
*/
+#define HOST_BRIDGE PCI_DEV(0, 0, 0)
+
#include "hostbridge_regs.h"
/*