usbdebug: Consolidate EHCI_BAR setup
There is assumption of static EHCI_BAR_INDEX, try to
clean it up by bringing BAR programming at one spot.
Change-Id: Ie16090536ac5470c24720a54813015250ae2d0dd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
diff --git a/src/drivers/usb/pci_ehci.c b/src/drivers/usb/pci_ehci.c
index de291ee..8b72f57 100644
--- a/src/drivers/usb/pci_ehci.c
+++ b/src/drivers/usb/pci_ehci.c
@@ -47,12 +47,18 @@
u32 cap = pci_read_config32(dev, pos);
/* FIXME: We should remove static EHCI_BAR_INDEX. */
- u8 dbg_bar = 0x10 + 4 * ((cap >> 29) - 1);
- if (dbg_bar != EHCI_BAR_INDEX)
+ u8 ehci_bar = 0x10 + 4 * ((cap >> 29) - 1);
+ if (ehci_bar != EHCI_BAR_INDEX)
return -1;
+ pci_write_config32(dev, ehci_bar, CONFIG_EHCI_BAR);
+
+ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY |
+ PCI_COMMAND_MASTER);
+
*base = CONFIG_EHCI_BAR;
*dbg_offset = (cap>>16) & 0x1ffc;
+
return 0;
}
diff --git a/src/soc/amd/stoneyridge/enable_usbdebug.c b/src/soc/amd/stoneyridge/enable_usbdebug.c
index 675f4b7..db1e4cf 100644
--- a/src/soc/amd/stoneyridge/enable_usbdebug.c
+++ b/src/soc/amd/stoneyridge/enable_usbdebug.c
@@ -53,8 +53,4 @@
/* Enable all of the USB controllers */
outb(0xEF, PM_INDEX);
outb(0x7F, PM_DATA);
-
- pci_write_config32(dev, EHCI_BAR_INDEX, base);
- pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY
- | PCI_COMMAND_MASTER);
}
diff --git a/src/soc/intel/broadwell/usb_debug.c b/src/soc/intel/broadwell/usb_debug.c
index 683b4cc..b19462d 100644
--- a/src/soc/intel/broadwell/usb_debug.c
+++ b/src/soc/intel/broadwell/usb_debug.c
@@ -41,12 +41,4 @@
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{
- if (!dev)
- return;
-
- /* Set the EHCI BAR address. */
- pci_write_config32(dev, EHCI_BAR_INDEX, base);
-
- /* Enable access to the EHCI memory space registers. */
- pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
}
diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
index fce7f5b..4a37e55 100644
--- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
+++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
@@ -53,7 +53,4 @@
/* Enable all of the USB controllers */
outb(0xEF, PM_INDEX);
outb(0x7F, PM_DATA);
-
- pci_write_config32(dev, EHCI_BAR_INDEX, base);
- pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
}
diff --git a/src/southbridge/amd/pi/hudson/enable_usbdebug.c b/src/southbridge/amd/pi/hudson/enable_usbdebug.c
index 787da6b..cb6961a 100644
--- a/src/southbridge/amd/pi/hudson/enable_usbdebug.c
+++ b/src/southbridge/amd/pi/hudson/enable_usbdebug.c
@@ -53,7 +53,4 @@
/* Enable all of the USB controllers */
outb(0xEF, PM_INDEX);
outb(0x7F, PM_DATA);
-
- pci_write_config32(dev, EHCI_BAR_INDEX, base);
- pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
}
diff --git a/src/southbridge/amd/sb600/enable_usbdebug.c b/src/southbridge/amd/sb600/enable_usbdebug.c
index 797f6d2..8b19cc4 100644
--- a/src/southbridge/amd/sb600/enable_usbdebug.c
+++ b/src/southbridge/amd/sb600/enable_usbdebug.c
@@ -35,9 +35,4 @@
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{
- /* Set the EHCI BAR address. */
- pci_write_config32(dev, EHCI_BAR_INDEX, base);
-
- /* Enable access to the EHCI memory space registers. */
- pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
}
diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c
index 22f730f..6d95b8e 100644
--- a/src/southbridge/amd/sb700/enable_usbdebug.c
+++ b/src/southbridge/amd/sb700/enable_usbdebug.c
@@ -48,10 +48,4 @@
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{
- /* Set the EHCI BAR address. */
- pci_write_config32(dev, EHCI_BAR_INDEX, base);
-
- /* Enable access to the EHCI memory space registers. */
- pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
-
}
diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c
index 3959ea8..8ef3151 100644
--- a/src/southbridge/amd/sb800/enable_usbdebug.c
+++ b/src/southbridge/amd/sb800/enable_usbdebug.c
@@ -53,7 +53,4 @@
/* Enable all of the USB controllers */
outb(0xEF, PM_INDEX);
outb(0x7F, PM_DATA);
-
- pci_write_config32(dev, EHCI_BAR_INDEX, base);
- pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
}
diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c
index eeac6d9..e1cd657 100644
--- a/src/southbridge/intel/common/usb_debug.c
+++ b/src/southbridge/intel/common/usb_debug.c
@@ -63,10 +63,4 @@
/* Bail out. No console to complain in. */
if (!dev)
return;
-
- /* Set the EHCI BAR address. */
- pci_write_config32(dev, EHCI_BAR_INDEX, base);
-
- /* Enable access to the EHCI memory space registers. */
- pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
}
diff --git a/src/southbridge/nvidia/ck804/enable_usbdebug.c b/src/southbridge/nvidia/ck804/enable_usbdebug.c
index 0f0e4cd..4ae4aa0 100644
--- a/src/southbridge/nvidia/ck804/enable_usbdebug.c
+++ b/src/southbridge/nvidia/ck804/enable_usbdebug.c
@@ -44,9 +44,4 @@
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{
- /* Set the EHCI BAR address. */
- pci_write_config32(dev, EHCI_BAR_INDEX, base);
-
- /* Enable access to the EHCI memory space registers. */
- pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
}
diff --git a/src/southbridge/nvidia/mcp55/enable_usbdebug.c b/src/southbridge/nvidia/mcp55/enable_usbdebug.c
index dfeb351..679a71d 100644
--- a/src/southbridge/nvidia/mcp55/enable_usbdebug.c
+++ b/src/southbridge/nvidia/mcp55/enable_usbdebug.c
@@ -44,9 +44,4 @@
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{
- /* Set the EHCI BAR address. */
- pci_write_config32(dev, EHCI_BAR_INDEX, base);
-
- /* Enable access to the EHCI memory space registers. */
- pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
}
diff --git a/src/southbridge/sis/sis966/enable_usbdebug.c b/src/southbridge/sis/sis966/enable_usbdebug.c
index 477f724..428af94 100644
--- a/src/southbridge/sis/sis966/enable_usbdebug.c
+++ b/src/southbridge/sis/sis966/enable_usbdebug.c
@@ -46,9 +46,4 @@
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{
- /* Set the EHCI BAR address. */
- pci_write_config32(dev, EHCI_BAR_INDEX, base);
-
- /* Enable access to the EHCI memory space registers. */
- pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
}