coreboot_tables: Add PCIe info to coreboot table
Add 'lb_fill_pcie' function to pass PCIe information from coreboot to
libpayload, and add CB_ERR_NOT_IMPLEMENTED to the cb_err enum for the
__weak function.
ARM platform usually does not have common address for PCIe to access the
configuration space of devices. Therefore, new API is added to pass the
base address of PCIe controller for payloads to access PCIe devices.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
BRANCH=cherry
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index 1d38c19..a8fd5cd 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -84,6 +84,7 @@
CB_TAG_ACPI_CNVS = 0x0041,
CB_TAG_TYPE_C_INFO = 0x0042,
CB_TAG_ACPI_RSDP = 0x0043,
+ CB_TAG_PCIE = 0x0044,
CB_TAG_CMOS_OPTION_TABLE = 0x00c8,
CB_TAG_OPTION = 0x00c9,
CB_TAG_OPTION_ENUM = 0x00ca,
@@ -265,6 +266,12 @@
struct cb_gpio gpios[0];
};
+struct cb_pcie {
+ uint32_t tag;
+ uint32_t size;
+ cb_uint64_t ctrl_base; /* Base address of PCIe controller */
+};
+
struct lb_range {
uint32_t tag;
uint32_t size;
diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h
index c8c1052..12d8a13 100644
--- a/payloads/libpayload/include/sysinfo.h
+++ b/payloads/libpayload/include/sysinfo.h
@@ -84,6 +84,7 @@
uintptr_t linker;
uintptr_t assembler;
uintptr_t mem_chip_base;
+ uintptr_t pcie_ctrl_base; /* Base address of PCIe controller */
uintptr_t cb_version;
diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c
index cdd6a43..bcc9530 100644
--- a/payloads/libpayload/libc/coreboot.c
+++ b/payloads/libpayload/libc/coreboot.c
@@ -264,6 +264,13 @@
}
}
+static void cb_parse_pcie(void *ptr, struct sysinfo_t *info)
+{
+ const struct cb_pcie *pcie = ptr;
+
+ info->pcie_ctrl_base = pcie->ctrl_base;
+}
+
static void cb_parse_rsdp(void *ptr, struct sysinfo_t *info)
{
const struct cb_acpi_rsdp *cb_acpi_rsdp = ptr;
@@ -413,6 +420,9 @@
case CB_TAG_ACPI_RSDP:
cb_parse_rsdp(ptr, info);
break;
+ case CB_TAG_PCIE:
+ cb_parse_pcie(ptr, info);
+ break;
default:
cb_parse_arch_specific(rec, info);
break;
diff --git a/src/commonlib/bsd/include/commonlib/bsd/cb_err.h b/src/commonlib/bsd/include/commonlib/bsd/cb_err.h
index eec44f2f..725882c 100644
--- a/src/commonlib/bsd/include/commonlib/bsd/cb_err.h
+++ b/src/commonlib/bsd/include/commonlib/bsd/cb_err.h
@@ -13,9 +13,10 @@
* success. Allocate a new group or errors every 100 values.
*/
enum cb_err {
- CB_SUCCESS = 0, /**< Call completed successfully */
- CB_ERR = -1, /**< Generic error code */
- CB_ERR_ARG = -2, /**< Invalid argument */
+ CB_SUCCESS = 0, /**< Call completed successfully */
+ CB_ERR = -1, /**< Generic error code */
+ CB_ERR_ARG = -2, /**< Invalid argument */
+ CB_ERR_NOT_IMPLEMENTED = -3, /**< Function not implemented */
/* NVRAM/CMOS errors */
CB_CMOS_OTABLE_DISABLED = -100, /**< Option table disabled */
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index 7666588..3f7ff2d 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -86,6 +86,7 @@
LB_TAG_ACPI_CNVS = 0x0041,
LB_TAG_TYPE_C_INFO = 0x0042,
LB_TAG_ACPI_RSDP = 0x0043,
+ LB_TAG_PCIE = 0x0044,
/* The following options are CMOS-related */
LB_TAG_CMOS_OPTION_TABLE = 0x00c8,
LB_TAG_OPTION = 0x00c9,
@@ -144,6 +145,14 @@
struct lb_memory_range map[0];
};
+struct lb_pcie {
+ uint32_t tag;
+ uint32_t size;
+ lb_uint64_t ctrl_base; /* Base address of PCIe controller */
+};
+_Static_assert(_Alignof(struct lb_pcie) == 4,
+ "lb_uint64_t alignment doesn't work as expected for struct lb_pcie!");
+
struct lb_hwrpb {
uint32_t tag;
uint32_t size;
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index e77c60a..7525fda 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -21,6 +21,8 @@
void lb_add_serial(struct lb_serial *serial, void *data);
void lb_add_console(uint16_t consoletype, void *data);
+enum cb_err lb_fill_pcie(struct lb_pcie *pcie);
+
/* Define this in mainboard.c to add board-specific table entries. */
void lb_board(struct lb_header *header);
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index ebaa3a5..2a7ccc5 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -33,6 +33,11 @@
void lb_string_platform_blob_version(struct lb_header *header);
#endif
+__weak enum cb_err lb_fill_pcie(struct lb_pcie *pcie)
+{
+ return CB_ERR_NOT_IMPLEMENTED;
+}
+
static struct lb_header *lb_table_init(unsigned long addr)
{
struct lb_header *header;
@@ -118,6 +123,16 @@
console->type = consoletype;
}
+static void lb_pcie(struct lb_header *header)
+{
+ struct lb_pcie pcie = { .tag = LB_TAG_PCIE, .size = sizeof(pcie) };
+
+ if (lb_fill_pcie(&pcie) != CB_SUCCESS)
+ return;
+
+ memcpy(lb_new_record(header), &pcie, sizeof(pcie));
+}
+
static void lb_framebuffer(struct lb_header *header)
{
struct lb_framebuffer *framebuffer;
@@ -483,6 +498,9 @@
if (CONFIG(CONSOLE_USB))
lb_add_console(LB_TAG_CONSOLE_EHCI, head);
+ if (CONFIG(PCI))
+ lb_pcie(head);
+
/* Record our various random string information */
lb_strings(head);
if (CONFIG(PLATFORM_USES_FSP2_0))