| commit | d165357ec37ce89ff4ee05f6d0bcfac6e766c1df | [log] [tgz] |
|---|---|---|
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | Tue Jun 08 11:31:19 2021 +0300 |
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | Thu Nov 10 19:10:42 2022 +0000 |
| tree | 70e3d2bcc856b7ec458b98561d485de538293da5 | |
| parent | c0457358f6ac47f8a771af474bb1987c74fb0cd6 [diff] [blame] |
sb,soc/intel: Use register_new_ioapic_gsi0() Change-Id: I6b0e4021595fb160ae3bf798468f4505b460266f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 1de3766..1569c1c 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c
@@ -50,7 +50,7 @@ pci_write_config32(dev, GEN_CNTL, reg32); printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); - setup_ioapic(VIO_APIC_VADDR, 0x02); + register_new_ioapic_gsi0(VIO_APIC_VADDR); ioapic_set_boot_config(VIO_APIC_VADDR, true); }