AMD binaryPI: Use madt_ioapic_from_hw()
Read IOAPIC ID and number of interrupts from programmed registers.
Change-Id: Ic8ba395bc220fdb691118719f7b32dd7400931f4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/src/northbridge/amd/pi/00730F01/acpi_tables.c b/src/northbridge/amd/pi/00730F01/acpi_tables.c
index bb510cd..ef240c1 100644
--- a/src/northbridge/amd/pi/00730F01/acpi_tables.c
+++ b/src/northbridge/amd/pi/00730F01/acpi_tables.c
@@ -3,7 +3,6 @@
#include <acpi/acpi.h>
#include <arch/ioapic.h>
#include <northbridge/amd/nb_common.h>
-#include <southbridge/amd/pi/hudson/ioapic.h>
unsigned long acpi_fill_madt(unsigned long current)
{
@@ -11,12 +10,10 @@
current = acpi_create_madt_lapics_with_nmis(current);
/* Write SB800 IOAPIC, only one */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, FCH_IOAPIC_ID,
- IO_APIC_ADDR, 0);
+ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR);
/* TODO: Remove the hardcode */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, GNB_IOAPIC_ID,
- IO_APIC2_ADDR, 24);
+ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC2_ADDR);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 0, 2, 0);
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index 644e2d5..5f3b4d9 100644
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -23,7 +23,6 @@
#include <northbridge/amd/nb_common.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <southbridge/amd/pi/hudson/pci_devs.h>
-#include <southbridge/amd/pi/hudson/ioapic.h>
#include <amdblocks/cpu.h>
#define MAX_NODE_NUMS MAX_NODES
@@ -222,7 +221,7 @@
static void northbridge_init(struct device *dev)
{
- setup_ioapic((u8 *)IO_APIC2_ADDR, GNB_IOAPIC_ID);
+ register_new_ioapic((u8 *)IO_APIC2_ADDR);
}
static unsigned long acpi_fill_hest(acpi_hest_t *hest)
@@ -254,17 +253,16 @@
ivhd_ioapic->dte_setting = IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS |
IVHD_DTE_SYS_MGT_NO_TRANS | IVHD_DTE_NMI_PASS |
IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS;
- ivhd_ioapic->handle = FCH_IOAPIC_ID;
+ ivhd_ioapic->handle = get_ioapic_id(VIO_APIC_VADDR);
ivhd_ioapic->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC);
ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC;
current += sizeof(ivrs_ivhd_special_t);
ivhd_ioapic = (ivrs_ivhd_special_t *)current;
-
ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV;
ivhd_ioapic->reserved = 0x0000;
ivhd_ioapic->dte_setting = 0x00;
- ivhd_ioapic->handle = GNB_IOAPIC_ID;
+ ivhd_ioapic->handle = get_ioapic_id((u8 *)IO_APIC2_ADDR);
ivhd_ioapic->source_dev_id = PCI_DEVFN(0, 1);
ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC;
current += sizeof(ivrs_ivhd_special_t);
diff --git a/src/northbridge/amd/pi/00730F01/state_machine.c b/src/northbridge/amd/pi/00730F01/state_machine.c
index 0693a5d..9128c24 100644
--- a/src/northbridge/amd/pi/00730F01/state_machine.c
+++ b/src/northbridge/amd/pi/00730F01/state_machine.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/biosram.h>
+#include <amdblocks/ioapic.h>
#include "Porting.h"
#include "AGESA.h"
@@ -9,7 +10,6 @@
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <northbridge/amd/nb_common.h>
-#include <southbridge/amd/pi/hudson/ioapic.h>
void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
{
diff --git a/src/southbridge/amd/pi/hudson/ioapic.h b/src/southbridge/amd/pi/hudson/ioapic.h
deleted file mode 100644
index 757e5c8..0000000
--- a/src/southbridge/amd/pi/hudson/ioapic.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef AMD_BLOCK_IOAPIC_H
-#define AMD_BLOCK_IOAPIC_H
-
-/* Since the old APIC bus isn't used any more, the IOAPIC IDs could be < CONFIG_MAX_CPUS */
-#define FCH_IOAPIC_ID (CONFIG_MAX_CPUS)
-#define GNB_IOAPIC_ID (CONFIG_MAX_CPUS + 1)
-
-#endif /* AMD_BLOCK_IOAPIC_H */
diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c
index c40bf5e..2dc2ae3 100644
--- a/src/southbridge/amd/pi/hudson/sm.c
+++ b/src/southbridge/amd/pi/hudson/sm.c
@@ -5,7 +5,6 @@
#include <device/pci_ids.h>
#include <device/smbus.h>
#include <arch/ioapic.h>
-#include <southbridge/amd/pi/hudson/ioapic.h>
#include "hudson.h"
#include "smbus.c"
@@ -22,7 +21,7 @@
static void sm_init(struct device *dev)
{
- setup_ioapic(VIO_APIC_VADDR, FCH_IOAPIC_ID);
+ register_new_ioapic_gsi0(VIO_APIC_VADDR);
}
static int lsmbus_recv_byte(struct device *dev)