nb/intel: Const'ify pci_devfn_t devices
Change-Id: Ib470523200929868280f57bb0cc82b038d2fedf6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c
index 92b2ae7..b1ac3d1 100644
--- a/src/northbridge/intel/e7505/memmap.c
+++ b/src/northbridge/intel/e7505/memmap.c
@@ -12,7 +12,7 @@
void *cbmem_top_chipset(void)
{
- pci_devfn_t mch = PCI_DEV(0, 0, 0);
+ const pci_devfn_t mch = PCI_DEV(0, 0, 0);
uintptr_t tolm;
/* This is at 128 MiB boundary. */
@@ -26,7 +26,7 @@
void northbridge_write_smram(u8 smram)
{
- pci_devfn_t mch = PCI_DEV(0, 0, 0);
+ const pci_devfn_t mch = PCI_DEV(0, 0, 0);
pci_write_config8(mch, SMRAMC, smram);
}
diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c
index 4226554..0d106b8 100644
--- a/src/northbridge/intel/gm45/iommu.c
+++ b/src/northbridge/intel/gm45/iommu.c
@@ -33,7 +33,7 @@
/* clear GTT */
u16 gtt = pci_read_config16(PCI_DEV(0, 0, 0), D0F0_GGC);
if (gtt & 0x400) { /* VT mode */
- pci_devfn_t igd = PCI_DEV(0, 2, 0);
+ const pci_devfn_t igd = PCI_DEV(0, 2, 0);
/* setup somewhere */
u8 cmd = pci_read_config8(igd, PCI_COMMAND);
@@ -52,7 +52,7 @@
if (stepping == STEPPING_B3) {
MCHBAR8(0xffc) |= 1 << 4;
- pci_devfn_t peg = PCI_DEV(0, 1, 0);
+ const pci_devfn_t peg = PCI_DEV(0, 1, 0);
/* FIXME: proper test? */
if (pci_read_config8(peg, PCI_CLASS_REVISION) != 0xff) {
int val = pci_read_config32(peg, 0xfc) | (1 << 15);