devicetree: Discriminate device ops scan_bus()
Use of scan_static_bus() and tree traversals is somewhat convoluted.
Start cleaning this up by assigning each path type with separate
static scan_bus() function.
For ME, SMBus and LPC paths a bus cannot expose bridges, as those would
add to the number of encountered PCI buses.
Change-Id: I8bb11450516faad4fa33b8f69bce5b9978ec75e5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8534
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c
index f3a525c..65cb955 100644
--- a/src/southbridge/amd/agesa/hudson/lpc.c
+++ b/src/southbridge/amd/agesa/hudson/lpc.c
@@ -333,7 +333,7 @@
#endif
.enable_resources = hudson_lpc_enable_resources,
.init = lpc_init,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_lpc_bus,
.ops_pci = &lops_pci,
};
static const struct pci_driver lpc_driver __pci_driver = {
diff --git a/src/southbridge/amd/agesa/hudson/sm.c b/src/southbridge/amd/agesa/hudson/sm.c
index fd8e6ad..09fbf8b 100644
--- a/src/southbridge/amd/agesa/hudson/sm.c
+++ b/src/southbridge/amd/agesa/hudson/sm.c
@@ -163,7 +163,7 @@
.set_resources = hudson_sm_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = sm_init,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_smbus,
.ops_pci = &lops_pci,
.ops_smbus_bus = &lops_smbus_bus,
};
diff --git a/src/southbridge/amd/amd8111/acpi.c b/src/southbridge/amd/amd8111/acpi.c
index 6d0ce26..396b7c4 100644
--- a/src/southbridge/amd/amd8111/acpi.c
+++ b/src/southbridge/amd/amd8111/acpi.c
@@ -226,7 +226,7 @@
.set_resources = pci_dev_set_resources,
.enable_resources = acpi_enable_resources,
.init = acpi_init,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_smbus,
/* We don't need amd8111_enable, chip ops takes care of it.
* It could be useful if these devices were not
* enabled by default.
diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c
index 2ded0cb..47b9ae7 100644
--- a/src/southbridge/amd/amd8111/lpc.c
+++ b/src/southbridge/amd/amd8111/lpc.c
@@ -151,7 +151,7 @@
.write_acpi_tables = acpi_write_hpet,
.acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator,
#endif
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_lpc_bus,
.enable = amd8111_enable,
.ops_pci = &lops_pci,
};
diff --git a/src/southbridge/amd/amd8111/smbus.c b/src/southbridge/amd/amd8111/smbus.c
index 0a0c58d..def1377 100644
--- a/src/southbridge/amd/amd8111/smbus.c
+++ b/src/southbridge/amd/amd8111/smbus.c
@@ -28,7 +28,7 @@
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = 0,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_smbus,
.enable = amd8111_enable,
.ops_pci = &lops_pci,
.ops_smbus_bus = &lops_smbus_bus,
diff --git a/src/southbridge/amd/amd8111/usb.c b/src/southbridge/amd/amd8111/usb.c
index 13dccf4..feb7793 100644
--- a/src/southbridge/amd/amd8111/usb.c
+++ b/src/southbridge/amd/amd8111/usb.c
@@ -25,8 +25,6 @@
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = 0,
- .scan_bus = scan_static_bus,
-// .enable = amd8111_enable,
.ops_pci = &lops_pci,
};
diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c
index 4254a5c..cd36fac 100644
--- a/src/southbridge/amd/cimx/sb700/late.c
+++ b/src/southbridge/amd/cimx/sb700/late.c
@@ -111,7 +111,7 @@
.write_acpi_tables = acpi_write_hpet,
#endif
.init = lpc_init,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_lpc_bus,
.ops_pci = &lops_pci,
};
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index 79c2203..0ada673 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -161,7 +161,7 @@
.write_acpi_tables = acpi_write_hpet,
#endif
.init = lpc_init,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_lpc_bus,
.ops_pci = &lops_pci,
};
diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c
index 7249ec5..fbff7df 100644
--- a/src/southbridge/amd/cimx/sb900/late.c
+++ b/src/southbridge/amd/cimx/sb900/late.c
@@ -132,7 +132,7 @@
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
.write_acpi_tables = acpi_write_hpet,
#endif
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_lpc_bus,
.ops_pci = &lops_pci,
};
diff --git a/src/southbridge/amd/cs5535/cs5535.c b/src/southbridge/amd/cs5535/cs5535.c
index e66a1e2..70b8386 100644
--- a/src/southbridge/amd/cs5535/cs5535.c
+++ b/src/southbridge/amd/cs5535/cs5535.c
@@ -94,7 +94,6 @@
.enable_resources = pci_dev_enable_resources,
.init = southbridge_init,
.enable = southbridge_enable,
- .scan_bus = scan_static_bus,
};
static const struct pci_driver cs5535_pci_driver __pci_driver = {
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index 0db8195..cece16d 100644
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -688,13 +688,18 @@
.read_byte = lsmbus_read_byte,
};
+static unsigned int scan_lpc_smbus(device_t dev, unsigned int max)
+{
+ /* FIXME. Do we have mixed LPC/SMBus device node here. */
+ return scan_smbus(dev, max);
+}
+
static struct device_operations southbridge_ops = {
.read_resources = cs5536_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = southbridge_init,
-// .enable = southbridge_enable,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_lpc_smbus,
.ops_smbus_bus = &lops_smbus_bus,
};
diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c
index 840ff7a..b813d12 100644
--- a/src/southbridge/amd/pi/hudson/lpc.c
+++ b/src/southbridge/amd/pi/hudson/lpc.c
@@ -340,7 +340,7 @@
.write_acpi_tables = acpi_write_hpet,
#endif
.init = lpc_init,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_lpc_bus,
.ops_pci = &lops_pci,
};
static const struct pci_driver lpc_driver __pci_driver = {
diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c
index fd8e6ad..09fbf8b 100644
--- a/src/southbridge/amd/pi/hudson/sm.c
+++ b/src/southbridge/amd/pi/hudson/sm.c
@@ -163,7 +163,7 @@
.set_resources = hudson_sm_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = sm_init,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_smbus,
.ops_pci = &lops_pci,
.ops_smbus_bus = &lops_smbus_bus,
};
diff --git a/src/southbridge/amd/sb600/lpc.c b/src/southbridge/amd/sb600/lpc.c
index 62c88de..2fb9e22 100644
--- a/src/southbridge/amd/sb600/lpc.c
+++ b/src/southbridge/amd/sb600/lpc.c
@@ -242,7 +242,7 @@
.acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator,
#endif
.init = lpc_init,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_lpc_bus,
/* .enable = sb600_enable, */
.ops_pci = &lops_pci,
};
diff --git a/src/southbridge/amd/sb600/sm.c b/src/southbridge/amd/sb600/sm.c
index 0254f83..40fde47 100644
--- a/src/southbridge/amd/sb600/sm.c
+++ b/src/southbridge/amd/sb600/sm.c
@@ -361,7 +361,7 @@
.set_resources = sb600_sm_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = sm_init,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_smbus,
/* .enable = sb600_enable, */
.ops_pci = &lops_pci,
.ops_smbus_bus = &lops_smbus_bus,
diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c
index be3c4d6..94d8dcb 100644
--- a/src/southbridge/amd/sb700/lpc.c
+++ b/src/southbridge/amd/sb700/lpc.c
@@ -287,7 +287,7 @@
.acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator,
#endif
.init = lpc_init,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_lpc_bus,
.ops_pci = &lops_pci,
};
static const struct pci_driver lpc_driver __pci_driver = {
diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c
index 2a88a80..f544c88 100644
--- a/src/southbridge/amd/sb700/sm.c
+++ b/src/southbridge/amd/sb700/sm.c
@@ -452,7 +452,7 @@
.set_resources = sb700_sm_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = sm_init,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_smbus,
.ops_pci = &lops_pci,
.ops_smbus_bus = &lops_smbus_bus,
};
diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c
index 5a40a8d..0cd5b32 100644
--- a/src/southbridge/amd/sb800/lpc.c
+++ b/src/southbridge/amd/sb800/lpc.c
@@ -254,7 +254,7 @@
.write_acpi_tables = acpi_write_hpet,
#endif
.init = lpc_init,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_lpc_bus,
.ops_pci = &lops_pci,
};
static const struct pci_driver lpc_driver __pci_driver = {
diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c
index b34cfbd..1523c60 100644
--- a/src/southbridge/amd/sb800/sm.c
+++ b/src/southbridge/amd/sb800/sm.c
@@ -343,7 +343,7 @@
.set_resources = sb800_sm_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = sm_init,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_smbus,
.ops_pci = &lops_pci,
.ops_smbus_bus = &lops_smbus_bus,
};
diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c
index 28e8a8f..ef70df6 100644
--- a/src/southbridge/broadcom/bcm5785/lpc.c
+++ b/src/southbridge/broadcom/bcm5785/lpc.c
@@ -135,7 +135,7 @@
.set_resources = pci_dev_set_resources,
.enable_resources = bcm5785_lpc_enable_resources,
.init = lpc_init,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_lpc_bus,
// .enable = bcm5785_enable,
.ops_pci = &lops_pci,
};
diff --git a/src/southbridge/broadcom/bcm5785/sb_pci_main.c b/src/southbridge/broadcom/bcm5785/sb_pci_main.c
index bddb090..3390b0d 100644
--- a/src/southbridge/broadcom/bcm5785/sb_pci_main.c
+++ b/src/southbridge/broadcom/bcm5785/sb_pci_main.c
@@ -154,7 +154,7 @@
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = sb_init,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_smbus,
// .enable = bcm5785_enable,
.ops_pci = &lops_pci,
.ops_smbus_bus = &lops_smbus_bus,
diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c
index 19b4757..192de74 100644
--- a/src/southbridge/dmp/vortex86ex/southbridge.c
+++ b/src/southbridge/dmp/vortex86ex/southbridge.c
@@ -619,7 +619,7 @@
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = &southbridge_init,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_lpc_bus,
.enable = 0,
.ops_pci = 0,
};
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index c1bc45f..fec0d5c 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -827,7 +827,7 @@
.init = lpc_init,
.final = lpc_final,
.enable = pch_lpc_enable,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_lpc_bus,
.ops_pci = &pci_ops,
};
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index ed25e44..ab3d475 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -760,7 +760,6 @@
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = intel_me_init,
- .scan_bus = scan_static_bus,
.ops_pci = &pci_ops,
};
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index 75e517f..6bd26c4 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -763,7 +763,6 @@
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = intel_me_init,
- .scan_bus = scan_static_bus,
.ops_pci = &pci_ops,
};
diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c
index 94546a7..0198841 100644
--- a/src/southbridge/intel/bd82x6x/smbus.c
+++ b/src/southbridge/intel/bd82x6x/smbus.c
@@ -151,7 +151,7 @@
.read_resources = smbus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_smbus,
.init = pch_smbus_init,
.ops_smbus_bus = &lops_smbus_bus,
.ops_pci = &smbus_pci_ops,
diff --git a/src/southbridge/intel/esb6300/lpc.c b/src/southbridge/intel/esb6300/lpc.c
index 22bb150..e1718bb 100644
--- a/src/southbridge/intel/esb6300/lpc.c
+++ b/src/southbridge/intel/esb6300/lpc.c
@@ -362,7 +362,7 @@
.set_resources = pci_dev_set_resources,
.enable_resources = esb6300_lpc_enable_resources,
.init = lpc_init,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_lpc_bus,
.enable = esb6300_enable,
.ops_pci = &lops_pci,
};
diff --git a/src/southbridge/intel/esb6300/smbus.c b/src/southbridge/intel/esb6300/smbus.c
index 92cb288..2c026b8 100644
--- a/src/southbridge/intel/esb6300/smbus.c
+++ b/src/southbridge/intel/esb6300/smbus.c
@@ -35,7 +35,7 @@
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = 0,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_smbus,
.enable = esb6300_enable,
.ops_pci = &lops_pci,
.ops_smbus_bus = &lops_smbus_bus,
diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c
index 1d92532..b410332 100644
--- a/src/southbridge/intel/fsp_bd82x6x/lpc.c
+++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c
@@ -761,7 +761,7 @@
.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
.init = lpc_init,
.enable = pch_lpc_enable,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_lpc_bus,
.ops_pci = &pci_ops,
};
diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c
index ab6ae09..8f65da3 100644
--- a/src/southbridge/intel/fsp_bd82x6x/me.c
+++ b/src/southbridge/intel/fsp_bd82x6x/me.c
@@ -759,7 +759,6 @@
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = intel_me_init,
- .scan_bus = scan_static_bus,
.ops_pci = &pci_ops,
};
diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
index 5e7b661..292dbba 100644
--- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
@@ -762,7 +762,6 @@
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = intel_me_init,
- .scan_bus = scan_static_bus,
.ops_pci = &pci_ops,
};
diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c
index 3aee7ed..22de62d 100644
--- a/src/southbridge/intel/fsp_rangeley/lpc.c
+++ b/src/southbridge/intel/fsp_rangeley/lpc.c
@@ -463,7 +463,7 @@
.write_acpi_tables = acpi_write_hpet,
.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
.enable = soc_lpc_enable,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_lpc_bus,
.ops_pci = &pci_ops,
};
diff --git a/src/southbridge/intel/fsp_rangeley/smbus.c b/src/southbridge/intel/fsp_rangeley/smbus.c
index 8368afe..7864b1e 100644
--- a/src/southbridge/intel/fsp_rangeley/smbus.c
+++ b/src/southbridge/intel/fsp_rangeley/smbus.c
@@ -87,7 +87,7 @@
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = 0,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_smbus,
.ops_smbus_bus = &lops_smbus_bus,
.ops_pci = &smbus_pci_ops,
};
diff --git a/src/southbridge/intel/i3100/lpc.c b/src/southbridge/intel/i3100/lpc.c
index b29180c..aef855f 100644
--- a/src/southbridge/intel/i3100/lpc.c
+++ b/src/southbridge/intel/i3100/lpc.c
@@ -457,7 +457,7 @@
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
.write_acpi_tables = acpi_write_hpet,
#endif
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_lpc_bus,
.enable = i3100_enable,
.ops_pci = &lops_pci,
};
diff --git a/src/southbridge/intel/i3100/smbus.c b/src/southbridge/intel/i3100/smbus.c
index 445b668..2feb00f 100644
--- a/src/southbridge/intel/i3100/smbus.c
+++ b/src/southbridge/intel/i3100/smbus.c
@@ -74,7 +74,7 @@
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = 0,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_smbus,
.enable = i3100_enable,
.ops_pci = &lops_pci,
.ops_smbus_bus = &lops_smbus_bus,
diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c
index 1945fae..024604b 100644
--- a/src/southbridge/intel/i82371eb/isa.c
+++ b/src/southbridge/intel/i82371eb/isa.c
@@ -145,7 +145,7 @@
.acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator,
#endif
.init = isa_init,
- .scan_bus = scan_static_bus, /* TODO: Needed? */
+ .scan_bus = scan_lpc_bus, /* TODO: Needed? */
.enable = 0,
.ops_pci = 0, /* No subsystem IDs on 82371EB! */
};
diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c
index 82647e1..3817357 100644
--- a/src/southbridge/intel/i82371eb/smbus.c
+++ b/src/southbridge/intel/i82371eb/smbus.c
@@ -121,7 +121,7 @@
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = 0,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_smbus,
.enable = pwrmgt_enable,
.ops_pci = 0, /* No subsystem IDs on 82371EB! */
.ops_smbus_bus = &lops_smbus_bus,
diff --git a/src/southbridge/intel/i82801ax/lpc.c b/src/southbridge/intel/i82801ax/lpc.c
index 4bd69d6..e960551 100644
--- a/src/southbridge/intel/i82801ax/lpc.c
+++ b/src/southbridge/intel/i82801ax/lpc.c
@@ -286,7 +286,7 @@
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = lpc_init,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_lpc_bus,
.enable = i82801ax_enable,
};
diff --git a/src/southbridge/intel/i82801ax/smbus.c b/src/southbridge/intel/i82801ax/smbus.c
index cbe9e4a..76a78d1 100644
--- a/src/southbridge/intel/i82801ax/smbus.c
+++ b/src/southbridge/intel/i82801ax/smbus.c
@@ -48,7 +48,7 @@
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = 0,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_smbus,
.enable = i82801ax_enable,
.ops_smbus_bus = &lops_smbus_bus,
};
diff --git a/src/southbridge/intel/i82801bx/lpc.c b/src/southbridge/intel/i82801bx/lpc.c
index edadf40..7247cdc 100644
--- a/src/southbridge/intel/i82801bx/lpc.c
+++ b/src/southbridge/intel/i82801bx/lpc.c
@@ -304,7 +304,7 @@
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = lpc_init,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_lpc_bus,
.enable = i82801bx_enable,
};
diff --git a/src/southbridge/intel/i82801bx/smbus.c b/src/southbridge/intel/i82801bx/smbus.c
index 8feb75b..836c256 100644
--- a/src/southbridge/intel/i82801bx/smbus.c
+++ b/src/southbridge/intel/i82801bx/smbus.c
@@ -48,7 +48,7 @@
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = 0,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_smbus,
.enable = i82801bx_enable,
.ops_smbus_bus = &lops_smbus_bus,
};
diff --git a/src/southbridge/intel/i82801cx/lpc.c b/src/southbridge/intel/i82801cx/lpc.c
index 22671c3..a348c95 100644
--- a/src/southbridge/intel/i82801cx/lpc.c
+++ b/src/southbridge/intel/i82801cx/lpc.c
@@ -230,7 +230,7 @@
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = lpc_init,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_lpc_bus,
.enable = 0,
};
diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c
index 9f2a23f..29a457a 100644
--- a/src/southbridge/intel/i82801dx/lpc.c
+++ b/src/southbridge/intel/i82801dx/lpc.c
@@ -336,7 +336,7 @@
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = lpc_init,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_lpc_bus,
.enable = i82801dx_enable,
};
diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c
index 0a2f6e3..630484a 100644
--- a/src/southbridge/intel/i82801ex/lpc.c
+++ b/src/southbridge/intel/i82801ex/lpc.c
@@ -369,7 +369,7 @@
.set_resources = pci_dev_set_resources,
.enable_resources = i82801ex_lpc_enable_resources,
.init = lpc_init,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_lpc_bus,
.enable = i82801ex_enable,
.ops_pci = &lops_pci,
};
diff --git a/src/southbridge/intel/i82801ex/smbus.c b/src/southbridge/intel/i82801ex/smbus.c
index fe49e11..75ea119 100644
--- a/src/southbridge/intel/i82801ex/smbus.c
+++ b/src/southbridge/intel/i82801ex/smbus.c
@@ -35,7 +35,7 @@
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = 0,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_smbus,
.enable = i82801ex_enable,
.ops_pci = &lops_pci,
.ops_smbus_bus = &lops_smbus_bus,
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index bf61855..5ff8c24 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -667,7 +667,7 @@
.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
.write_acpi_tables = acpi_write_hpet,
.init = lpc_init,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_lpc_bus,
.enable = i82801gx_enable,
.ops_pci = &pci_ops,
};
diff --git a/src/southbridge/intel/i82801gx/smbus.c b/src/southbridge/intel/i82801gx/smbus.c
index 585d16c..e556d72 100644
--- a/src/southbridge/intel/i82801gx/smbus.c
+++ b/src/southbridge/intel/i82801gx/smbus.c
@@ -258,7 +258,7 @@
.read_resources = smbus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_smbus,
.enable = i82801gx_enable,
.ops_smbus_bus = &lops_smbus_bus,
.ops_pci = &smbus_pci_ops,
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index 3cc053b..8713e55 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -582,7 +582,7 @@
.write_acpi_tables = acpi_write_hpet,
.acpi_fill_ssdt_generator = southbridge_fill_ssdt,
.init = lpc_init,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_lpc_bus,
.ops_pci = &pci_ops,
};
diff --git a/src/southbridge/intel/i82801ix/smbus.c b/src/southbridge/intel/i82801ix/smbus.c
index 635cb19..9ae267d 100644
--- a/src/southbridge/intel/i82801ix/smbus.c
+++ b/src/southbridge/intel/i82801ix/smbus.c
@@ -101,7 +101,7 @@
.read_resources = smbus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_smbus,
.init = pch_smbus_init,
.ops_smbus_bus = &lops_smbus_bus,
.ops_pci = &smbus_pci_ops,
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index f066b35..e46bea6 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -805,7 +805,7 @@
.write_acpi_tables = acpi_write_hpet,
.init = lpc_init,
.enable = pch_lpc_enable,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_lpc_bus,
.ops_pci = &pci_ops,
};
diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c
index e68bb01..96e16e3 100644
--- a/src/southbridge/intel/ibexpeak/me.c
+++ b/src/southbridge/intel/ibexpeak/me.c
@@ -634,7 +634,6 @@
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = intel_me_init,
- .scan_bus = scan_static_bus,
.ops_pci = &pci_ops,
};
diff --git a/src/southbridge/intel/ibexpeak/smbus.c b/src/southbridge/intel/ibexpeak/smbus.c
index 085aec0..2bb4cbf 100644
--- a/src/southbridge/intel/ibexpeak/smbus.c
+++ b/src/southbridge/intel/ibexpeak/smbus.c
@@ -108,7 +108,7 @@
.read_resources = smbus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_smbus,
.init = pch_smbus_init,
.ops_smbus_bus = &lops_smbus_bus,
.ops_pci = &smbus_pci_ops,
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index c055da5..4b7de54 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -834,7 +834,7 @@
.write_acpi_tables = southbridge_write_acpi_tables,
.init = lpc_init,
.enable = pch_lpc_enable,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_lpc_bus,
.ops_pci = &pci_ops,
};
diff --git a/src/southbridge/intel/lynxpoint/smbus.c b/src/southbridge/intel/lynxpoint/smbus.c
index ae16a92..b7c8503 100644
--- a/src/southbridge/intel/lynxpoint/smbus.c
+++ b/src/southbridge/intel/lynxpoint/smbus.c
@@ -155,7 +155,7 @@
.read_resources = smbus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_smbus,
.init = pch_smbus_init,
.ops_smbus_bus = &lops_smbus_bus,
.ops_pci = &smbus_pci_ops,
diff --git a/src/southbridge/intel/sch/lpc.c b/src/southbridge/intel/sch/lpc.c
index e40b051..e961e4f 100644
--- a/src/southbridge/intel/sch/lpc.c
+++ b/src/southbridge/intel/sch/lpc.c
@@ -222,7 +222,7 @@
.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
.write_acpi_tables = acpi_write_hpet,
.init = lpc_init,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_lpc_bus,
.ops_pci = &pci_ops,
};
diff --git a/src/southbridge/intel/sch/smbus.c b/src/southbridge/intel/sch/smbus.c
index d208fcc..c3bff67 100644
--- a/src/southbridge/intel/sch/smbus.c
+++ b/src/southbridge/intel/sch/smbus.c
@@ -65,7 +65,7 @@
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = 0,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_smbus,
.ops_smbus_bus = &lops_smbus_bus,
.ops_pci = &smbus_pci_ops,
};
diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c
index c6f8c24..406b4f2 100644
--- a/src/southbridge/nvidia/ck804/lpc.c
+++ b/src/southbridge/nvidia/ck804/lpc.c
@@ -329,7 +329,7 @@
.write_acpi_tables = acpi_write_hpet,
#endif
.init = lpc_init,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_lpc_bus,
.ops_pci = &ck804_pci_ops,
};
diff --git a/src/southbridge/nvidia/ck804/smbus.c b/src/southbridge/nvidia/ck804/smbus.c
index f5fa1d5..2803df0 100644
--- a/src/southbridge/nvidia/ck804/smbus.c
+++ b/src/southbridge/nvidia/ck804/smbus.c
@@ -96,7 +96,7 @@
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = 0,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_smbus,
.ops_pci = &ck804_pci_ops,
.ops_smbus_bus = &lops_smbus_bus,
};
diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c
index d9c6211..d3399f3 100644
--- a/src/southbridge/nvidia/mcp55/lpc.c
+++ b/src/southbridge/nvidia/mcp55/lpc.c
@@ -261,7 +261,7 @@
.set_resources = pci_dev_set_resources,
.enable_resources = mcp55_lpc_enable_resources,
.init = lpc_init,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_lpc_bus,
// .enable = mcp55_enable,
.ops_pci = &mcp55_pci_ops,
};
diff --git a/src/southbridge/nvidia/mcp55/smbus.c b/src/southbridge/nvidia/mcp55/smbus.c
index 91d5830..2a56069 100644
--- a/src/southbridge/nvidia/mcp55/smbus.c
+++ b/src/southbridge/nvidia/mcp55/smbus.c
@@ -127,7 +127,7 @@
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = mcp55_sm_init,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_smbus,
// .enable = mcp55_enable,
.ops_pci = &mcp55_pci_ops,
.ops_smbus_bus = &lops_smbus_bus,
diff --git a/src/southbridge/rdc/r8610/r8610.c b/src/southbridge/rdc/r8610/r8610.c
index 338a133..328f3be 100644
--- a/src/southbridge/rdc/r8610/r8610.c
+++ b/src/southbridge/rdc/r8610/r8610.c
@@ -105,7 +105,6 @@
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = &southbridge_init,
- .scan_bus = scan_static_bus,
.enable = 0,
.ops_pci = 0,
};
diff --git a/src/southbridge/sis/sis966/lpc.c b/src/southbridge/sis/sis966/lpc.c
index 9194420..e5eaa06 100644
--- a/src/southbridge/sis/sis966/lpc.c
+++ b/src/southbridge/sis/sis966/lpc.c
@@ -259,7 +259,7 @@
.set_resources = pci_dev_set_resources,
.enable_resources = sis966_lpc_enable_resources,
.init = lpc_init,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_lpc_bus,
// .enable = sis966_enable,
.ops_pci = &lops_pci,
};
diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index ebaaa04..f7f2dbe 100644
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -657,7 +657,7 @@
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = vt8237s_init,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_lpc_bus,
.ops_pci = &lops_pci,
};
@@ -666,7 +666,7 @@
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = vt8237r_init,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_lpc_bus,
.ops_pci = &lops_pci,
};
@@ -675,7 +675,7 @@
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = vt8237a_init,
- .scan_bus = scan_static_bus,
+ .scan_bus = scan_lpc_bus,
.ops_pci = &lops_pci,
};