vc/intel/fsp/mtl: Update header files from 3292.83 to 3323.84
Update header files for FSP for Meteor Lake platform from 3292.83
to 3323.84.
The patch changess only a few spacing alignment for FSP-M header and
added few PPR (Post Package Repair) related variable for MemInfoHob
header.
BUG=b:297965979
TEST=Able to build and boot google/rex.
Change-Id: I65c6e05256a2ae9516449dbce62affd040cb0e56
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77561
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h
index b69beba..1835b54 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h
@@ -1214,8 +1214,8 @@
UINT8 Avx2RatioOffset;
/** Offset 0x0403 - AVX3 Ratio Offset
- 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
- vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
+ DEPRECATED. 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease
+ AVX ratio vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
**/
UINT8 Avx3RatioOffset;
@@ -2793,7 +2793,7 @@
/** Offset 0x0C4A - Reserved
**/
- UINT8 Reserved66[2];
+ UINT8 Reserved66[2];
/** Offset 0x0C4C - BCLK RFI Frequency
Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz <b>0 - No
@@ -3016,8 +3016,8 @@
UINT8 Avx2VoltageScaleFactor;
/** Offset 0x0DD8 - Avx512 Voltage Guardband Scaling Factor
- AVX512 Voltage Guardband Scale factor applied to AVX512 workloads. Range is 0-200
- in 1/100 units, where a value of 125 would apply a 1.25 scale factor.
+ DEPRECATED. AVX512 Voltage Guardband Scale factor applied to AVX512 workloads. Range
+ is 0-200 in 1/100 units, where a value of 125 would apply a 1.25 scale factor.
**/
UINT8 Avx512VoltageScaleFactor;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/MemInfoHob.h
index d28ed89..7660a30 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/MemInfoHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/MemInfoHob.h
@@ -187,7 +187,7 @@
UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
- UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
+ UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
UINT16 tCCD_L_WR; ///< Number of tCK cycles for the channel DIMM's minimum Write-to-Write delay for same bank group.
} MRC_CH_TIMING;
@@ -203,7 +203,7 @@
UINT8 DimmId;
UINT32 DimmCapacity; ///< DIMM size in MBytes.
UINT16 MfgId;
- UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
+ UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DDR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
UINT8 RankInDimm; ///< The number of ranks in this DIMM.
UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
@@ -285,6 +285,9 @@
HOB_SAGV_INFO SagvConfigInfo; ///< This data structure contains SAGV config values that are considered output by the MRC.
BOOLEAN IsIbeccEnabled;
UINT16 TotalMemWidth; ///< Total Memory Width in bits from all populated channels
+ UINT16 PprDetectedErrors; ///< PPR: Counts of detected bad rows
+ UINT16 PprRepairFails; ///< PPR: Counts of repair failure
+ UINT16 PprForceRepairStatus; ///< PPR: Force Repair Status
} MEMORY_INFO_DATA_HOB;
/**