soc/intel/broadwell: Align raminit with Haswell
Rename and split functions to match what Haswell does.
Change-Id: I4f3e997dd934bdf7717a70603d9413eae93cf181
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h
index ebef2c8..8a9953b 100644
--- a/src/soc/intel/broadwell/include/soc/romstage.h
+++ b/src/soc/intel/broadwell/include/soc/romstage.h
@@ -8,7 +8,9 @@
void mainboard_fill_spd_data(struct pei_data *pei_data);
void mainboard_post_raminit(const int s3resume);
-void raminit(struct pei_data *pei_data);
+void sdram_initialize(struct pei_data *pei_data);
+void save_mrc_data(struct pei_data *pei_data);
+void setup_sdram_meminfo(struct pei_data *pei_data);
struct chipset_power_state;
struct chipset_power_state *fill_power_state(void);
diff --git a/src/soc/intel/broadwell/raminit.c b/src/soc/intel/broadwell/raminit.c
index 506c6f6..1c9d440 100644
--- a/src/soc/intel/broadwell/raminit.c
+++ b/src/soc/intel/broadwell/raminit.c
@@ -16,6 +16,17 @@
#include <soc/romstage.h>
#include <soc/systemagent.h>
+void save_mrc_data(struct pei_data *pei_data)
+{
+ printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->data_to_save,
+ pei_data->data_to_save_size);
+
+ if (pei_data->data_to_save != NULL && pei_data->data_to_save_size > 0)
+ mrc_cache_stash_data(MRC_TRAINING_DATA, 0,
+ pei_data->data_to_save,
+ pei_data->data_to_save_size);
+}
+
static const char *const ecc_decoder[] = {
"inactive",
"active on IO",
@@ -69,10 +80,9 @@
/*
* Find PEI executable in coreboot filesystem and execute it.
*/
-void raminit(struct pei_data *pei_data)
+void sdram_initialize(struct pei_data *pei_data)
{
size_t mrc_size;
- struct memory_info *mem_info;
pei_wrapper_entry_t entry;
int ret;
@@ -125,22 +135,11 @@
(version >> 8) & 0xff, (version >> 0) & 0xff);
report_memory_config();
+}
- if (pei_data->boot_mode != ACPI_S3) {
- cbmem_initialize_empty();
- } else if (cbmem_initialize()) {
- printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
- /* Failed S3 resume, reset to come up cleanly */
- system_reset();
- }
-
- printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->data_to_save,
- pei_data->data_to_save_size);
-
- if (pei_data->data_to_save != NULL && pei_data->data_to_save_size > 0)
- mrc_cache_stash_data(MRC_TRAINING_DATA, 0,
- pei_data->data_to_save,
- pei_data->data_to_save_size);
+void setup_sdram_meminfo(struct pei_data *pei_data)
+{
+ struct memory_info *mem_info;
printk(BIOS_DEBUG, "create cbmem for dimm information\n");
mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info));
diff --git a/src/soc/intel/broadwell/romstage.c b/src/soc/intel/broadwell/romstage.c
index d33156e..33b4e4a 100644
--- a/src/soc/intel/broadwell/romstage.c
+++ b/src/soc/intel/broadwell/romstage.c
@@ -2,6 +2,8 @@
#include <acpi/acpi.h>
#include <arch/romstage.h>
+#include <cbmem.h>
+#include <cf9_reset.h>
#include <console/console.h>
#include <cpu/intel/haswell/haswell.h>
#include <elog.h>
@@ -67,10 +69,22 @@
&power_state->hsio_checksum);
/* Initialize RAM */
- raminit(&pei_data);
+ sdram_initialize(&pei_data);
timestamp_add_now(TS_AFTER_INITRAM);
+ if (pei_data.boot_mode != ACPI_S3) {
+ cbmem_initialize_empty();
+ } else if (cbmem_initialize()) {
+ printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
+ /* Failed S3 resume, reset to come up cleanly */
+ system_reset();
+ }
+
+ save_mrc_data(&pei_data);
+
+ setup_sdram_meminfo(&pei_data);
+
romstage_handoff_init(power_state->prev_sleep_state == ACPI_S3);
mainboard_post_raminit(power_state->prev_sleep_state == ACPI_S3);