mb/supermicro: Add X9SAE and X9SAE-V
Mainboard information can be found in the included documentation.
Change-Id: I9dfc58bb99e14cd9dac2ac53afc0ea11d2252aa9
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
diff --git a/src/mainboard/supermicro/x9sae/Kconfig b/src/mainboard/supermicro/x9sae/Kconfig
new file mode 100644
index 0000000..4afe85e
--- /dev/null
+++ b/src/mainboard/supermicro/x9sae/Kconfig
@@ -0,0 +1,31 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_SUPERMICRO_X9SAE
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_16384
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select HAVE_CMOS_DEFAULT
+ select HAVE_OPTION_TABLE
+ select INTEL_GMA_HAVE_VBT
+ select INTEL_INT15
+ select MAINBOARD_HAS_LIBGFXINIT
+ select MAINBOARD_HAS_LPC_TPM
+ select MAINBOARD_USES_IFD_GBE_REGION
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_C216
+ select SUPERIO_NUVOTON_NCT6776
+ select USE_NATIVE_RAMINIT
+
+config MAINBOARD_DIR
+ string
+ default "supermicro/x9sae"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "X9SAE"
+
+endif
diff --git a/src/mainboard/supermicro/x9sae/Kconfig.name b/src/mainboard/supermicro/x9sae/Kconfig.name
new file mode 100644
index 0000000..566dce8
--- /dev/null
+++ b/src/mainboard/supermicro/x9sae/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_SUPERMICRO_X9SAE
+ bool "X9SAE"
diff --git a/src/mainboard/supermicro/x9sae/Makefile.inc b/src/mainboard/supermicro/x9sae/Makefile.inc
new file mode 100644
index 0000000..5310efd
--- /dev/null
+++ b/src/mainboard/supermicro/x9sae/Makefile.inc
@@ -0,0 +1,8 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += early_init.c
+bootblock-y += gpio.c
+romstage-y += early_init.c
+romstage-y += gpio.c
+ramstage-y += hda_verb.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/supermicro/x9sae/acpi/ec.asl b/src/mainboard/supermicro/x9sae/acpi/ec.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/supermicro/x9sae/acpi/ec.asl
diff --git a/src/mainboard/supermicro/x9sae/acpi/pci.asl b/src/mainboard/supermicro/x9sae/acpi/pci.asl
new file mode 100644
index 0000000..72b497c
--- /dev/null
+++ b/src/mainboard/supermicro/x9sae/acpi/pci.asl
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// Intel PCI to PCI bridge 0:1e.0
+
+Device (PCIB)
+{
+ Name (_ADR, 0x001E0000) // _ADR: Address
+ Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake
+
+ Method (_PRT) // _PRT: PCI Interrupt Routing Table
+ {
+ If (PICM) {
+ Return (Package() {
+ Package() { 0x0001ffff, 0, 0, 0x16 },
+ Package() { 0x0001ffff, 1, 0, 0x15 },
+ Package() { 0x0001ffff, 2, 0, 0x14 },
+ Package() { 0x0001ffff, 3, 0, 0x13 },
+ Package() { 0x0002ffff, 0, 0, 0x12 },
+ Package() { 0x0002ffff, 1, 0, 0x13 },
+ Package() { 0x0002ffff, 2, 0, 0x11 },
+ Package() { 0x0002ffff, 3, 0, 0x10 },
+ Package() { 0x0003ffff, 0, 0, 0x13 },
+ Package() { 0x0003ffff, 1, 0, 0x12 },
+ Package() { 0x0003ffff, 2, 0, 0x15 },
+ Package() { 0x0003ffff, 3, 0, 0x16 },
+ Package() { 0x0000ffff, 0, 0, 0x10 },
+ Package() { 0x0000ffff, 1, 0, 0x11 },
+ Package() { 0x0000ffff, 2, 0, 0x12 },
+ Package() { 0x0000ffff, 3, 0, 0x13 },
+ })
+ }
+ Return (Package() {
+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
+ Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
+ Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKE, 0 },
+ Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0 },
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+ Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+ Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 },
+ Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKG, 0 },
+ Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+ })
+ }
+}
diff --git a/src/mainboard/supermicro/x9sae/acpi/platform.asl b/src/mainboard/supermicro/x9sae/acpi/platform.asl
new file mode 100644
index 0000000..aff432b
--- /dev/null
+++ b/src/mainboard/supermicro/x9sae/acpi/platform.asl
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method(_WAK, 1)
+{
+ Return(Package() {0, 0})
+}
+
+Method(_PTS, 1)
+{
+}
diff --git a/src/mainboard/supermicro/x9sae/acpi/superio.asl b/src/mainboard/supermicro/x9sae/acpi/superio.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/supermicro/x9sae/acpi/superio.asl
diff --git a/src/mainboard/supermicro/x9sae/board_info.txt b/src/mainboard/supermicro/x9sae/board_info.txt
new file mode 100644
index 0000000..3ff778f
--- /dev/null
+++ b/src/mainboard/supermicro/x9sae/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://www.supermicro.com/products/motherboard/xeon/c216/x9sae.cfm
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: Occasionally
+Flashrom support: y
+Release year: 2012
diff --git a/src/mainboard/supermicro/x9sae/cmos.default b/src/mainboard/supermicro/x9sae/cmos.default
new file mode 100644
index 0000000..c7aa620
--- /dev/null
+++ b/src/mainboard/supermicro/x9sae/cmos.default
@@ -0,0 +1,6 @@
+boot_option=Fallback
+debug_level=Debug
+nmi=Disable
+power_on_after_fail=Disable
+sata_mode=AHCI
+gfx_uma_size=64M
diff --git a/src/mainboard/supermicro/x9sae/cmos.layout b/src/mainboard/supermicro/x9sae/cmos.layout
new file mode 100644
index 0000000..0f9de5e
--- /dev/null
+++ b/src/mainboard/supermicro/x9sae/cmos.layout
@@ -0,0 +1,86 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 2 boot_option
+388 4 h 0 reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395 4 e 3 debug_level
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+
+409 2 e 4 power_on_after_fail
+411 2 e 5 sata_mode
+
+# coreboot config options: northbridge
+416 5 e 6 gfx_uma_size
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+#ID value text
+
+# Generic on/off enum
+1 0 Disable
+1 1 Enable
+
+# boot_option
+2 0 Fallback
+2 1 Normal
+
+# debug_level
+3 0 Emergency
+3 1 Alert
+3 2 Critical
+3 3 Error
+3 4 Warning
+3 5 Notice
+3 6 Info
+3 7 Debug
+3 8 Spew
+
+# power_on_after_fail
+4 0 Disable
+4 1 Enable
+4 2 Keep
+
+# sata_mode
+5 0 AHCI
+5 1 Compatible
+5 2 Legacy
+
+# gfx_uma_size (Intel IGP Video RAM size)
+6 0 32M
+6 1 64M
+6 2 96M
+6 3 128M
+6 4 160M
+6 5 192M
+6 6 224M
+6 7 256M
+6 8 288M
+6 9 320M
+6 10 352M
+6 11 384M
+6 12 416M
+6 13 448M
+6 14 480M
+6 15 512M
+6 16 1024M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 423 984
diff --git a/src/mainboard/supermicro/x9sae/data.vbt b/src/mainboard/supermicro/x9sae/data.vbt
new file mode 100644
index 0000000..1a0d233
--- /dev/null
+++ b/src/mainboard/supermicro/x9sae/data.vbt
Binary files differ
diff --git a/src/mainboard/supermicro/x9sae/devicetree.cb b/src/mainboard/supermicro/x9sae/devicetree.cb
new file mode 100644
index 0000000..05a187e
--- /dev/null
+++ b/src/mainboard/supermicro/x9sae/devicetree.cb
@@ -0,0 +1,125 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip northbridge/intel/sandybridge
+ register "gfx" = "GMA_STATIC_DISPLAYS(0)"
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_dp_d_hotplug" = "4"
+ register "gpu_panel_power_cycle_delay" = "4"
+ device cpu_cluster 0 on
+ chip cpu/intel/model_206ax
+ register "acpi_c1" = "1"
+ register "acpi_c2" = "3"
+ register "acpi_c3" = "5"
+ device lapic 0 on end
+ device lapic 0xacac off end
+ end
+ end
+ device domain 0 on
+ subsystemid 0x15d9 0x0644 inherit
+
+ device pci 00.0 on end # Host bridge
+ device pci 01.0 on end # CPU1 SLOT6 (x8 or x16)
+ device pci 01.1 on end # CPU1 SLOT4 (electrical x8 in x16 if present)
+ device pci 02.0 on end # iGPU
+ device pci 06.0 on end # CPU1 SLOT7 (electrical x4 in x8)
+
+ chip southbridge/intel/bd82x6x
+ register "gen1_dec" = "0x00fc0a01" # NCT6776 SuperIO (0x0a00-0aff)
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x3f"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x00000c03"
+ register "xhci_switchable_ports" = "0x0000000f"
+
+ device pci 14.0 on end # xHCI
+ device pci 16.0 on end # MEI #1
+ device pci 16.1 off end # MEI #2
+ device pci 16.2 off end # ME IDE-R
+ device pci 16.3 off end # ME KT
+ device pci 19.0 on end # Intel GbE LAN1
+ device pci 1a.0 on end # EHCI #2
+ device pci 1b.0 on end # HD Audio
+
+ device pci 1c.0 on end # RP #1 PCH SLOT2
+ device pci 1c.1 off end # RP #2
+ device pci 1c.2 off end # RP #3
+ device pci 1c.3 off end # RP #4
+ device pci 1c.4 on end # RP #5 PCH SLOT3
+ device pci 1c.5 off end # RP #6
+ device pci 1c.6 on end # RP #7 PCH SLOT5
+ device pci 1c.7 on # RP #8
+ device pci 00.0 on end # 574 GbE LAN2
+ end
+
+ device pci 1d.0 on end # EHCI #1
+ device pci 1e.0 on end # PCI bridge
+ device pci 1f.0 on # LPC bridge
+ chip superio/nuvoton/nct6776
+ device pnp 2e.0 off end # Floppy
+ device pnp 2e.1 off end # Parallel port
+ device pnp 2e.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # COM2, IR
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x060
+ io 0x62 = 0x064
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 off end # GPIO6
+ device pnp 2e.107 off end # GPIO7
+ device pnp 2e.207 off end # GPIO8
+ device pnp 2e.307 off end # GPIO9
+ device pnp 2e.8 off end # WDT
+ device pnp 2e.108 on end # GPIO0
+ device pnp 2e.208 off end # GPIOA
+ device pnp 2e.308 on # GPIOBASE
+ io 0x60 = 0xa00
+ end
+ device pnp 2e.109 off end # GPIO1
+ device pnp 2e.209 on end # GPIO2
+ device pnp 2e.309 off end # GPIO3
+ device pnp 2e.409 off end # GPIO4
+ device pnp 2e.509 off end # GPIO5
+ device pnp 2e.609 off end # GPIO6
+ device pnp 2e.709 off end # GPIO7
+ device pnp 2e.a on # ACPI
+ irq 0xe0 = 0
+ irq 0xe4 = 0x60
+ irq 0xe6 = 0x4c
+ irq 0xe7 = 0x10
+ irq 0xf2 = 0x5d
+ end
+ device pnp 2e.b on # HWM, front panel LED
+ io 0x60 = 0xa30
+ io 0x62 = 0xa80
+ irq 0x70 = 0
+ irq 0xf8 = 0x43
+ end
+ device pnp 2e.d off end # VID
+ device pnp 2e.e off end # CIR WAKE-UP
+ device pnp 2e.f off end # GPIO
+ device pnp 2e.14 off end # SVID
+ device pnp 2e.16 off end # Deep sleep
+ device pnp 2e.17 off end # GPIOA
+ end
+ chip drivers/pc80/tpm
+ device pnp c31.0 on end # TPM
+ end
+ end
+ device pci 1f.2 on end # SATA (AHCI)
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # SATA (Legacy)
+ device pci 1f.6 off end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/supermicro/x9sae/dsdt.asl b/src/mainboard/supermicro/x9sae/dsdt.asl
new file mode 100644
index 0000000..77577de
--- /dev/null
+++ b/src/mainboard/supermicro/x9sae/dsdt.asl
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ ACPI_DSDT_REV_2,
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 /* OEM revision */
+)
+{
+ #include <acpi/dsdt_top.asl>
+ #include "acpi/platform.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/common/acpi/platform.asl>
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ #include "acpi/pci.asl"
+ }
+}
diff --git a/src/mainboard/supermicro/x9sae/early_init.c b/src/mainboard/supermicro/x9sae/early_init.c
new file mode 100644
index 0000000..7e03212
--- /dev/null
+++ b/src/mainboard/supermicro/x9sae/early_init.c
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pnp_ops.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6776/nct6776.h>
+
+#define GLOBAL_DEV PNP_DEV(0x2e, 0)
+#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
+#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI)
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 0, 0 },
+ { 1, 0, 0 },
+ { 1, 0, 1 },
+ { 1, 0, 1 },
+ { 1, 0, 2 },
+ { 1, 0, 2 },
+ { 1, 0, 3 },
+ { 1, 0, 3 },
+ { 1, 0, 4 },
+ { 1, 0, 4 },
+ { 1, 0, 6 },
+ { 1, 0, 5 },
+ { 1, 0, 5 },
+ { 1, 0, 6 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
+
+ /* Select SIO pin states */
+ pnp_write_config(GLOBAL_DEV, 0x1a, 0xc8);
+ pnp_write_config(GLOBAL_DEV, 0x1b, 0x6d);
+ pnp_write_config(GLOBAL_DEV, 0x1c, 0x83);
+ pnp_write_config(GLOBAL_DEV, 0x24, 0x24);
+ pnp_write_config(GLOBAL_DEV, 0x2a, 0x00);
+ pnp_write_config(GLOBAL_DEV, 0x2b, 0x02);
+ pnp_write_config(GLOBAL_DEV, 0x2c, 0x80);
+
+ /* Power RAM in S3 */
+ pnp_set_logical_device(ACPI_DEV);
+ pnp_write_config(ACPI_DEV, 0xe4, 0x10);
+
+ pnp_set_logical_device(SERIAL_DEV);
+
+ nuvoton_pnp_exit_conf_state(GLOBAL_DEV);
+
+ /* Enable UART */
+ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[1], 0x51, id_only);
+ read_spd(&spd[2], 0x52, id_only);
+ read_spd(&spd[3], 0x53, id_only);
+}
diff --git a/src/mainboard/supermicro/x9sae/gma-mainboard.ads b/src/mainboard/supermicro/x9sae/gma-mainboard.ads
new file mode 100644
index 0000000..8b07c07
--- /dev/null
+++ b/src/mainboard/supermicro/x9sae/gma-mainboard.ads
@@ -0,0 +1,17 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (HDMI1,
+ HDMI2,
+ Analog,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/supermicro/x9sae/gpio.c b/src/mainboard/supermicro/x9sae/gpio.c
new file mode 100644
index 0000000..6cb163f
--- /dev/null
+++ b/src/mainboard/supermicro/x9sae/gpio.c
@@ -0,0 +1,190 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_NATIVE,
+ .gpio3 = GPIO_MODE_NATIVE,
+ .gpio4 = GPIO_MODE_NATIVE,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_NATIVE,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_NATIVE,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_OUTPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_OUTPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_OUTPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_OUTPUT,
+ .gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio14 = GPIO_LEVEL_LOW,
+ .gpio21 = GPIO_LEVEL_HIGH,
+ .gpio24 = GPIO_LEVEL_HIGH,
+ .gpio27 = GPIO_LEVEL_HIGH,
+ .gpio28 = GPIO_LEVEL_LOW,
+ .gpio29 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio0 = GPIO_INVERT,
+ .gpio1 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_GPIO,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_NATIVE,
+ .gpio37 = GPIO_MODE_NATIVE,
+ .gpio38 = GPIO_MODE_NATIVE,
+ .gpio39 = GPIO_MODE_NATIVE,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_GPIO,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_GPIO,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_NATIVE,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_NATIVE,
+ .gpio52 = GPIO_MODE_NATIVE,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_NATIVE,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_NATIVE,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_OUTPUT,
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio35 = GPIO_DIR_OUTPUT,
+ .gpio44 = GPIO_DIR_OUTPUT,
+ .gpio45 = GPIO_DIR_OUTPUT,
+ .gpio46 = GPIO_DIR_OUTPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio32 = GPIO_LEVEL_HIGH,
+ .gpio33 = GPIO_LEVEL_HIGH,
+ .gpio35 = GPIO_LEVEL_HIGH,
+ .gpio44 = GPIO_LEVEL_HIGH,
+ .gpio45 = GPIO_LEVEL_HIGH,
+ .gpio46 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_GPIO,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+ .gpio72 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/supermicro/x9sae/hda_verb.c b/src/mainboard/supermicro/x9sae/hda_verb.c
new file mode 100644
index 0000000..5feb741
--- /dev/null
+++ b/src/mainboard/supermicro/x9sae/hda_verb.c
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10ec0889, /* Codec Vendor / Device ID: Realtek */
+ 0x15d90644, /* Subsystem ID */
+ 15, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x15d90644),
+ AZALIA_PIN_CFG(0, 0x11, 0x18561120),
+ AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x14, 0x01014010),
+ AZALIA_PIN_CFG(0, 0x15, 0x01011012),
+ AZALIA_PIN_CFG(0, 0x16, 0x01016011),
+ AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x18, 0x01a19840),
+ AZALIA_PIN_CFG(0, 0x19, 0x02a19841),
+ AZALIA_PIN_CFG(0, 0x1a, 0x0181344f),
+ AZALIA_PIN_CFG(0, 0x1b, 0x0221401f),
+ AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1d, 0x4007e619),
+ AZALIA_PIN_CFG(0, 0x1e, 0x01452130),
+ AZALIA_PIN_CFG(0, 0x1f, 0x01c41150),
+
+ 0x80862806, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+ AZALIA_PIN_CFG(3, 0x05, 0x58560010),
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/supermicro/x9sae/mainboard.c b/src/mainboard/supermicro/x9sae/mainboard.c
new file mode 100644
index 0000000..4322c1e
--- /dev/null
+++ b/src/mainboard/supermicro/x9sae/mainboard.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+static void mainboard_enable(struct device *dev)
+{
+ /* FIXME: fix these values. */
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};