SATA: Add option to configure gen3 transmitter
Unfortunately the drive strength values are very much board
specific and different between mobile and desktop so we don't
try to do any fancy detection here but let it be specified
directly in the devicetree.
Change-Id: I66674bff0de04ecd088fb09afad1cf801a374df2
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/1347
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index 880244b..07a2af7 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -67,6 +67,8 @@
uint32_t ide_legacy_combined;
uint32_t sata_ahci;
uint8_t sata_port_map;
+ uint32_t sata_port0_gen3_tx;
+ uint32_t sata_port1_gen3_tx;
uint32_t gen1_dec;
uint32_t gen2_dec;
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 0a16308..beed63a 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -198,6 +198,10 @@
#define SATA_SP 0xd0 /* Scratchpad */
+/* SATA IOBP Registers */
+#define SATA_IOBP_SP0G3IR 0xea000151
+#define SATA_IOBP_SP1G3IR 0xea000051
+
/* PCI Configuration Space (D31:F3): SMBus */
#define PCH_SMBUS_DEV PCI_DEV(0, 0x1f, 3)
#define SMB_BASE 0x20
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index c0eb232..2e41158 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -182,6 +182,15 @@
pci_write_config32(dev, 0x94,
((config->sata_port_map ^ 0x3f) << 24) | 0x183);
}
+
+ /* Set Gen3 Transmitter settings if needed */
+ if (config->sata_port0_gen3_tx)
+ pch_iobp_update(SATA_IOBP_SP0G3IR, 0,
+ config->sata_port0_gen3_tx);
+
+ if (config->sata_port1_gen3_tx)
+ pch_iobp_update(SATA_IOBP_SP1G3IR, 0,
+ config->sata_port1_gen3_tx);
}
static void sata_enable(device_t dev)